From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39C80C33CA1 for ; Wed, 5 Feb 2020 09:54:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 16DC02051A for ; Wed, 5 Feb 2020 09:54:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728194AbgBEJy0 convert rfc822-to-8bit (ORCPT ); Wed, 5 Feb 2020 04:54:26 -0500 Received: from relay9-d.mail.gandi.net ([217.70.183.199]:44347 "EHLO relay9-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727170AbgBEJy0 (ORCPT ); Wed, 5 Feb 2020 04:54:26 -0500 X-Originating-IP: 90.76.211.102 Received: from xps13 (lfbn-tou-1-1151-102.w90-76.abo.wanadoo.fr [90.76.211.102]) (Authenticated sender: miquel.raynal@bootlin.com) by relay9-d.mail.gandi.net (Postfix) with ESMTPSA id C24A8FF80F; Wed, 5 Feb 2020 09:54:22 +0000 (UTC) Date: Wed, 5 Feb 2020 10:54:22 +0100 From: Miquel Raynal To: shiva.linuxworks@gmail.com Cc: Richard Weinberger , Vignesh Raghavendra , Frieder Schrempf , Boris Brezillon , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Shivamurthy Shastri Subject: Re: [PATCH v3 4/5] mtd: spinand: micron: Add M70A series Micron SPI NAND devices Message-ID: <20200205105422.57b5f6c4@xps13> In-Reply-To: <20200202215508.2928-5-sshivamurthy@micron.com> References: <20200202215508.2928-1-sshivamurthy@micron.com> <20200202215508.2928-5-sshivamurthy@micron.com> Organization: Bootlin X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi shiva.linuxworks@gmail.com, shiva.linuxworks@gmail.com wrote on Sun, 2 Feb 2020 22:55:07 +0100: > From: Shivamurthy Shastri > > Add device table for M70A series Micron SPI NAND devices. > > As opposed to the M79A and M78A series already supported, M70A parts > have the "Continuous Read" feature enabled by default, which does not fit > the subsystem needs. > > In this mode, the READ CACHE command doesn't require the starting column > address. The device always output the data starting from the first > column of the cache register, and once the end of the cache register > reached, the data output continues through the next page. With the > continuous read mode, it is possible to read out the entire block using > a single READ command, and once the end of the block reached, the output > pins become High-Z state. However, during this mode the read command > doesn't output the OOB area. > > Hence, we disable the feature at probe time. > > Signed-off-by: Shivamurthy Shastri > --- > drivers/mtd/nand/spi/micron.c | 36 +++++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c > index 5fd1f921ef12..3d3734afc35e 100644 > --- a/drivers/mtd/nand/spi/micron.c > +++ b/drivers/mtd/nand/spi/micron.c > @@ -18,6 +18,8 @@ > #define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4) > #define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4) > > +#define MICRON_CFG_CONTI_READ BIT(0) > + > static SPINAND_OP_VARIANTS(read_cache_variants, > SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), > SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), > @@ -131,6 +133,26 @@ static const struct spinand_info micron_spinand_table[] = { > 0, > SPINAND_ECCINFO(µn_8_ooblayout, > micron_8_ecc_get_status)), > + /* M70A 4Gb 3.3V */ > + SPINAND_INFO("MT29F4G01ABAFD", 0x34, > + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), > + NAND_ECCREQ(8, 512), > + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, > + &write_cache_variants, > + &update_cache_variants), > + SPINAND_HAS_CR_FEAT_BIT, > + SPINAND_ECCINFO(µn_8_ooblayout, > + micron_8_ecc_get_status)), > + /* M70A 4Gb 1.8V */ > + SPINAND_INFO("MT29F4G01ABBFD", 0x35, > + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), > + NAND_ECCREQ(8, 512), > + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, > + &write_cache_variants, > + &update_cache_variants), > + SPINAND_HAS_CR_FEAT_BIT, > + SPINAND_ECCINFO(µn_8_ooblayout, > + micron_8_ecc_get_status)), > }; > > static int micron_spinand_detect(struct spinand_device *spinand) > @@ -153,8 +175,22 @@ static int micron_spinand_detect(struct spinand_device *spinand) > return 1; > } > > +static int micron_spinand_init(struct spinand_device *spinand) > +{ > + /* > + * M70A device series enable Continuous Read feature at Power-up, > + * which is not supported. Disable this bit to avoid any possible > + * failure. > + */ > + if (spinand->flags == SPINAND_HAS_CR_FEAT_BIT) > + return spinand_upd_cfg(spinand, MICRON_CFG_CONTI_READ, 0); > + > + return 0; > +} > + > static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = { > .detect = micron_spinand_detect, > + .init = micron_spinand_init, > }; I would move the addition of .init = ... and the function definition to patch 3/5. The logic is: 1/ You introduce the feature 2/ You add support for new devices and use this feature > > const struct spinand_manufacturer micron_spinand_manufacturer = { Otherwise looks good. Thanks, Miquèl