From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B9DDC35640 for ; Fri, 21 Feb 2020 09:08:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 61923208C4 for ; Fri, 21 Feb 2020 09:08:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="VllRnzbB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727976AbgBUJI4 (ORCPT ); Fri, 21 Feb 2020 04:08:56 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:43696 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727833AbgBUJIx (ORCPT ); Fri, 21 Feb 2020 04:08:53 -0500 Received: by mail-wr1-f65.google.com with SMTP id r11so1075348wrq.10 for ; Fri, 21 Feb 2020 01:08:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sBEY6IZdpR56nXsPUK2cFqYc8DeNfrXDbwpY0flDUNU=; b=VllRnzbBY6hzEcF2hDDNEkEEdYvCxAauRWNfmMJ2jr5QM+kqIiikup1MAhGL9zBWyd oUrboYCfNKZ4a0skJ6d7MgewVYHeestIVqUH2cy6fY9JY5Dp1e1L36ssdzJyMbUD5yHw 1CxyhZVKgDm7TzzTjLpeFiJZHRmDCyGqwZNUa7BP7UXCKEM4eRiEJNOPd9TCyc+DhR7T P/m11SbBi7RnlEU9hGAED2brqYRm9OeMYaYVLjRvREON2AI04lMe+5L1W+qWdHiOafHY G8FzRy3/4Bagi6LkMZ8zrki3MjALcwD60jngmtaK3e4xoYe2zvTnMfs1uHPgD4wLxuIW 1KWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sBEY6IZdpR56nXsPUK2cFqYc8DeNfrXDbwpY0flDUNU=; b=h1CLzjc48KaWrup9aukRFyA+ppGq8+x/HDPeIldYqSh8zsMsZp87HQMbtaSED3DMKQ 2Z4TJhk7CUGGozk+goMztEKOIsNNFK0mtz0Ri7ubI6vd3aXfSZDjHvjyYsamDfRfp3A6 NgY5NOaSr4lESDKaOQEf+HjaEo1fxvDGIl0+EOE261zvXws0ubjt8WYZv/xwFDYOQzwK Gg9iOXAA2Kta7NCzhavVEaxmQiXT88TZ0stb5G821oUOl+u6PbrEj1fQGOOQ8lmsE6IQ jHOnlPq5WtQ0R2lnfBkKp9/0cY0C2ee3Zd+Wbx4hMAU3MGqYRYGonxHa6NEU3ISGDGRh 3OCA== X-Gm-Message-State: APjAAAVizt3OiXaLJ4JDi3skxpWattTur0gZwIkHH6TGbPk5XDMO3e+a PJeQLDl4uaSCSAAtayJwUUdRbA== X-Google-Smtp-Source: APXvYqzkjc9uO1jlQ9asSGYblHXAZ61o5tYA+NmLBT/SG0XjoMfflPRxU5alISIHTeI3dAaRbSoJkg== X-Received: by 2002:a5d:6692:: with SMTP id l18mr45917500wru.382.1582276131114; Fri, 21 Feb 2020 01:08:51 -0800 (PST) Received: from bender.baylibre.local ([2a01:e35:2ec0:82b0:4ca8:b25b:98e4:858]) by smtp.gmail.com with ESMTPSA id h5sm3173288wmf.8.2020.02.21.01.08.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 01:08:50 -0800 (PST) From: Neil Armstrong To: daniel@ffwll.ch, dri-devel@lists.freedesktop.org Cc: Neil Armstrong , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] drm/meson: add Amlogic Video FBC registers Date: Fri, 21 Feb 2020 10:08:43 +0100 Message-Id: <20200221090845.7397-3-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200221090845.7397-1-narmstrong@baylibre.com> References: <20200221090845.7397-1-narmstrong@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the registers of the VPU VD1 Amlogic FBC decoder module, and routing register. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_registers.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h index 8ea00546cd4e..08631fdfe4b9 100644 --- a/drivers/gpu/drm/meson/meson_registers.h +++ b/drivers/gpu/drm/meson/meson_registers.h @@ -144,10 +144,15 @@ #define VIU_SW_RESET_OSD1 BIT(0) #define VIU_MISC_CTRL0 0x1a06 #define VIU_CTRL0_VD1_AFBC_MASK 0x170000 +#define VIU_CTRL0_AFBC_TO_VD1 BIT(20) #define VIU_MISC_CTRL1 0x1a07 #define MALI_AFBC_MISC GENMASK(15, 8) #define D2D3_INTF_LENGTH 0x1a08 #define D2D3_INTF_CTRL0 0x1a09 +#define VD1_AFBCD0_MISC_CTRL 0x1a0a +#define VD1_AXI_SEL_AFBC (1 << 12) +#define AFBC_VD1_SEL (1 << 10) +#define VD2_AFBCD1_MISC_CTRL 0x1a0b #define VIU_OSD1_CTRL_STAT 0x1a10 #define VIU_OSD1_OSD_BLK_ENABLE BIT(0) #define VIU_OSD1_OSD_MEM_MODE_LINEAR BIT(2) @@ -365,6 +370,23 @@ #define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add #define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade #define AFBC_ENABLE 0x1ae0 +#define AFBC_MODE 0x1ae1 +#define AFBC_SIZE_IN 0x1ae2 +#define AFBC_DEC_DEF_COLOR 0x1ae3 +#define AFBC_CONV_CTRL 0x1ae4 +#define AFBC_LBUF_DEPTH 0x1ae5 +#define AFBC_HEAD_BADDR 0x1ae6 +#define AFBC_BODY_BADDR 0x1ae7 +#define AFBC_SIZE_OUT 0x1ae8 +#define AFBC_OUT_YSCOPE 0x1ae9 +#define AFBC_STAT 0x1aea +#define AFBC_VD_CFMT_CTRL 0x1aeb +#define AFBC_VD_CFMT_W 0x1aec +#define AFBC_MIF_HOR_SCOPE 0x1aed +#define AFBC_MIF_VER_SCOPE 0x1aee +#define AFBC_PIXEL_HOR_SCOPE 0x1aef +#define AFBC_PIXEL_VER_SCOPE 0x1af0 +#define AFBC_VD_CFMT_H 0x1af1 /* vpp */ #define VPP_DUMMY_DATA 0x1d00 -- 2.22.0