From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47AB2C3F2D2 for ; Fri, 28 Feb 2020 16:21:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 170412467B for ; Fri, 28 Feb 2020 16:21:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1582906862; bh=n1275XsDQKYhS7LmjOu+E8pP5RdHGFNfW11MWKAQ9u8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=l3CJ7/XcyfrWPJqCFIcTj6UktzCiab1WmdY1efNZvyLJB3hJ/ZCkPZjZvG6QVAwAS 4MPgcDanaETNPfSvpLQ1P+WHC0gLvpgAOfB2oT3CeyJLu1CIjkPew4rYueJVoWjKQc De5Sph4qgJX688rqfym4QRAdhljR42hcShwJmgD0= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726418AbgB1QVA (ORCPT ); Fri, 28 Feb 2020 11:21:00 -0500 Received: from foss.arm.com ([217.140.110.172]:40920 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725730AbgB1QVA (ORCPT ); Fri, 28 Feb 2020 11:21:00 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ED7B431B; Fri, 28 Feb 2020 08:20:59 -0800 (PST) Received: from localhost (unknown [10.37.6.21]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6FBA73F73B; Fri, 28 Feb 2020 08:20:59 -0800 (PST) Date: Fri, 28 Feb 2020 16:20:57 +0000 From: Mark Brown To: John Garry Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, andriy.shevchenko@linux.intel.com, linuxarm@huawei.com Subject: Re: [PATCH RFC 3/3] spi: HiSilicon v3xx: Use DMI quirk to set controller buswidth override bits Message-ID: <20200228162057.GC4956@sirena.org.uk> References: <1582903131-160033-1-git-send-email-john.garry@huawei.com> <1582903131-160033-4-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="DSayHWYpDlRfCAAQ" Content-Disposition: inline In-Reply-To: <1582903131-160033-4-git-send-email-john.garry@huawei.com> X-Cookie: There Is No Cabal. User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --DSayHWYpDlRfCAAQ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Feb 28, 2020 at 11:18:51PM +0800, John Garry wrote: > The Huawei D06 board (and variants) can support Quad mode of operation. >=20 > Since we have no current method in ACPI SPI bus device resource descripti= on > to describe this information, use DMI to detect the board, and set the > controller buswidth override bits. Hopefully this is something that the ACPI people will be looking to address going forwards :/ --DSayHWYpDlRfCAAQ Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAl5ZPekACgkQJNaLcl1U h9BxUwf/TDuNgCXr7WDgjO72Sd8M518jpCW63B2SJ/nhlOul+uSQtPp38AvFbOKG xdPHKVoh82UV1cn6w79H71fMVmDy3y9uPlIB+GTxvnGze9F03HHo0ybJuAD6pvmb gW4TsG3xZ9TatTMfM5n3sc0APvcfxXe3DjqWOhsdw9zlGddgfpObtyTApRiScQWK UBZQnih2B8Fkgfbb5QSCjMEuxd4Hwp6lz/EkxKbBvgG3m8H41ONev6XKRkPCNagd 8tS65tJb0nhEuP6X8F0NpkkyQaDwsWSybWp06Zo8X1f5E2yxdhgc0qCbPThGFnil f30KtWcvkDjZRu0eymnJ+Zab1jvEHQ== =T+F5 -----END PGP SIGNATURE----- --DSayHWYpDlRfCAAQ--