From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89A35C10F29 for ; Tue, 17 Mar 2020 07:28:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5CD0420674 for ; Tue, 17 Mar 2020 07:28:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Bg7XNRfQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726575AbgCQH2Y (ORCPT ); Tue, 17 Mar 2020 03:28:24 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:43984 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725783AbgCQH2W (ORCPT ); Tue, 17 Mar 2020 03:28:22 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02H7SG5E106100; Tue, 17 Mar 2020 02:28:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584430096; bh=pfOH4ox5Paw4s1ADE2d3H27U4ycp6Cba0NtZ1NV3DM4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Bg7XNRfQZjWOSQ9hDVj66xttWEg7r6T8+u7qwxm2U9H8VdgT/VrcBYMcK9iU1IBPK oj53euGEccnKKaif/9EKYiN3iDN/YXZSQIvLapbZ4YvPplsQdYvo1Apc0gqRG9wMuw e85foKzq+3c5T0yQtV3t96+UIGO1/q8CazGcp/O8= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 02H7SGI5027469 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 17 Mar 2020 02:28:16 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Tue, 17 Mar 2020 02:28:16 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Tue, 17 Mar 2020 02:28:16 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02H7SFtE092588; Tue, 17 Mar 2020 02:28:15 -0500 From: Grygorii Strashko To: Rob Herring , Kishon Vijay Abraham I , Tero Kristo , "David S . Miller" , netdev , Roger Quadros , , Jakub Kicinski CC: Murali Karicheri , Sekhar Nori , Peter Ujfalusi , , , Grygorii Strashko Subject: [PATCH net-next v4 04/11] net: ethernet: ti: ale: am65: add support for default thread cfg Date: Tue, 17 Mar 2020 09:27:32 +0200 Message-ID: <20200317072739.23950-5-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200317072739.23950-1-grygorii.strashko@ti.com> References: <20200317072739.23950-1-grygorii.strashko@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for default thread configuration for AM65x CPSW NUSS ALE to allow route all ingress packets to one default RX UDMA flow. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw_ale.c | 18 ++++++++++++++++++ drivers/net/ethernet/ti/cpsw_ale.h | 2 ++ 2 files changed, 20 insertions(+) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 719e7846127c..0374e6936091 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -44,6 +44,8 @@ #define ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS 0x9C #define ALE_VLAN_MASK_MUX(reg) (0xc0 + (0x4 * (reg))) +#define AM65_CPSW_ALE_THREAD_DEF_REG 0x134 + #define ALE_TABLE_WRITE BIT(31) #define ALE_TYPE_FREE 0 @@ -843,6 +845,22 @@ static struct ale_control_info ale_controls[ALE_NUM_CONTROLS] = { .port_shift = 0, .bits = 6, }, + [ALE_DEFAULT_THREAD_ID] = { + .name = "default_thread_id", + .offset = AM65_CPSW_ALE_THREAD_DEF_REG, + .port_offset = 0, + .shift = 0, + .port_shift = 0, + .bits = 6, + }, + [ALE_DEFAULT_THREAD_ENABLE] = { + .name = "default_thread_id_enable", + .offset = AM65_CPSW_ALE_THREAD_DEF_REG, + .port_offset = 0, + .shift = 15, + .port_shift = 0, + .bits = 1, + }, }; int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control, diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index eaca73c17ae7..6a3cb6898728 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -66,6 +66,8 @@ enum cpsw_ale_control { ALE_PORT_MACONLY_CAF, ALE_PORT_BCAST_LIMIT, ALE_PORT_MCAST_LIMIT, + ALE_DEFAULT_THREAD_ID, + ALE_DEFAULT_THREAD_ENABLE, ALE_NUM_CONTROLS, }; -- 2.17.1