From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1E3BC2BB1D for ; Tue, 17 Mar 2020 23:30:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 871C720714 for ; Tue, 17 Mar 2020 23:30:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727223AbgCQXaG (ORCPT ); Tue, 17 Mar 2020 19:30:06 -0400 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:48641 "EHLO alexa-out-sd-02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727150AbgCQXaG (ORCPT ); Tue, 17 Mar 2020 19:30:06 -0400 Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 17 Mar 2020 16:30:05 -0700 Received: from gurus-linux.qualcomm.com ([10.46.162.81]) by ironmsg05-sd.qualcomm.com with ESMTP; 17 Mar 2020 16:30:05 -0700 Received: by gurus-linux.qualcomm.com (Postfix, from userid 383780) id ABB1E4BA2; Tue, 17 Mar 2020 16:30:05 -0700 (PDT) Date: Tue, 17 Mar 2020 16:30:05 -0700 From: Guru Das Srinagesh To: Arnd Bergmann Cc: Linux PWM List , Thierry Reding , Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= , Subbaraman Narayanamurthy , "linux-kernel@vger.kernel.org" , Alexander Shiyan Subject: Re: [PATCH v9 04/11] pwm: clps711x: Use 64-bit division macro Message-ID: <20200317233003.GA11350@codeaurora.org> References: <587f9ccae68ad7e1ce97fa8da6037292af1a5095.1584473399.git.gurus@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 17, 2020 at 11:22:06PM +0100, Arnd Bergmann wrote: > > diff --git a/drivers/pwm/pwm-clps711x.c b/drivers/pwm/pwm-clps711x.c > > index 924d39a..ba9500a 100644 > > --- a/drivers/pwm/pwm-clps711x.c > > +++ b/drivers/pwm/pwm-clps711x.c > > @@ -43,7 +43,7 @@ static void clps711x_pwm_update_val(struct clps711x_chip *priv, u32 n, u32 v) > > static unsigned int clps711x_get_duty(struct pwm_device *pwm, unsigned int v) > > { > > /* Duty cycle 0..15 max */ > > - return DIV_ROUND_CLOSEST(v * 0xf, pwm->args.period); > > + return DIV64_U64_ROUND_CLOSEST(v * 0xf, pwm->args.period); > > } > > Is it actually going to exceed U32_MAX? If not, a type cast may be > more appropriate here than the expensive 64-bit division. With the final change in this patch series, the framework will support periods that exceed U32_MAX. My concern is that using a typecast would mean that in those cases, this driver will not support > U32_MAX values. Using DIV64_U64_ROUND_CLOSEST makes the driver future proof and able to handle > U32_MAX values correctly. What do you think? Thank you. Guru Das.