mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: kbuild test robot <lkp@intel.com>
To: Yang Weijiang <weijiang.yang@intel.com>
Cc: kbuild-all@lists.01.org, kvm@vger.kernel.org,
	linux-kernel@vger.kernel.org, sean.j.christopherson@intel.com,
	pbonzini@redhat.com, jmattson@google.com
Subject: Re: [PATCH v10 6/8] KVM: X86: Add userspace access interface for CET MSRs
Date: Fri, 20 Mar 2020 23:48:17 +0800	[thread overview]
Message-ID: <202003202309.SvJfslTC%lkp@intel.com> (raw)
In-Reply-To: <20200320034342.26610-7-weijiang.yang@intel.com>

Hi Yang,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on kvm/linux-next]
[also build test WARNING on next-20200319]
[cannot apply to vhost/linux-next tip/auto-latest linux/master linus/master v5.6-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Yang-Weijiang/Introduce-support-for-guest-CET-feature/20200320-155517
base:   https://git.kernel.org/pub/scm/virt/kvm/kvm.git linux-next
reproduce:
        # apt-get install sparse
        # sparse version: v0.6.1-181-g83789bbc-dirty
        make ARCH=x86_64 allmodconfig
        make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>


sparse warnings: (new ones prefixed by >>)

   arch/x86/kvm/x86.c:809:60: sparse: sparse: undefined identifier 'X86_CR4_CET'
   arch/x86/kvm/x86.c:1233:23: sparse: sparse: undefined identifier 'MSR_IA32_U_CET'
   arch/x86/kvm/x86.c:1233:39: sparse: sparse: undefined identifier 'MSR_IA32_S_CET'
   arch/x86/kvm/x86.c:1234:9: sparse: sparse: undefined identifier 'MSR_IA32_PL0_SSP'
   arch/x86/kvm/x86.c:1234:27: sparse: sparse: undefined identifier 'MSR_IA32_PL1_SSP'
   arch/x86/kvm/x86.c:1234:45: sparse: sparse: undefined identifier 'MSR_IA32_PL2_SSP'
   arch/x86/kvm/x86.c:1235:9: sparse: sparse: undefined identifier 'MSR_IA32_PL3_SSP'
   arch/x86/kvm/x86.c:1235:27: sparse: sparse: undefined identifier 'MSR_IA32_INT_SSP_TAB'
   arch/x86/kvm/x86.c:1512:14: sparse: sparse: undefined identifier 'MSR_IA32_PL0_SSP'
   arch/x86/kvm/x86.c:1512:35: sparse: sparse: undefined identifier 'MSR_IA32_PL3_SSP'
   arch/x86/kvm/x86.c:1513:14: sparse: sparse: undefined identifier 'MSR_IA32_U_CET'
   arch/x86/kvm/x86.c:1514:14: sparse: sparse: undefined identifier 'MSR_IA32_S_CET'
   arch/x86/kvm/x86.c:1515:14: sparse: sparse: undefined identifier 'MSR_IA32_INT_SSP_TAB'
>> arch/x86/kvm/x86.c:1512:14: sparse: sparse: incompatible types for 'case' statement
   arch/x86/kvm/x86.c:1512:35: sparse: sparse: incompatible types for 'case' statement
   arch/x86/kvm/x86.c:1513:14: sparse: sparse: incompatible types for 'case' statement
   arch/x86/kvm/x86.c:1514:14: sparse: sparse: incompatible types for 'case' statement
   arch/x86/kvm/x86.c:1515:14: sparse: sparse: incompatible types for 'case' statement
   arch/x86/kvm/x86.c:2646:38: sparse: sparse: incorrect type in argument 1 (different address spaces) @@    expected void const [noderef] <asn:1> * @@    got  const [noderef] <asn:1> * @@
   arch/x86/kvm/x86.c:2646:38: sparse:    expected void const [noderef] <asn:1> *
   arch/x86/kvm/x86.c:2646:38: sparse:    got unsigned char [usertype] *
   arch/x86/kvm/x86.c:3267:25: sparse: sparse: undefined identifier 'MSR_IA32_U_CET'
   arch/x86/kvm/x86.c:7549:15: sparse: sparse: incompatible types in comparison expression (different address spaces):
   arch/x86/kvm/x86.c:7549:15: sparse:    struct kvm_apic_map [noderef] <asn:4> *
   arch/x86/kvm/x86.c:7549:15: sparse:    struct kvm_apic_map *
   arch/x86/kvm/x86.c:9678:44: sparse: sparse: undefined identifier 'XFEATURE_MASK_CET_USER'
   arch/x86/kvm/x86.c:9678:44: sparse: sparse: undefined identifier 'XFEATURE_MASK_CET_KERNEL'
   arch/x86/kvm/x86.c:9912:16: sparse: sparse: incompatible types in comparison expression (different address spaces):
   arch/x86/kvm/x86.c:9912:16: sparse:    struct kvm_apic_map [noderef] <asn:4> *
   arch/x86/kvm/x86.c:9912:16: sparse:    struct kvm_apic_map *
   arch/x86/kvm/x86.c:9913:15: sparse: sparse: incompatible types in comparison expression (different address spaces):
   arch/x86/kvm/x86.c:9913:15: sparse:    struct kvm_pmu_event_filter [noderef] <asn:4> *
   arch/x86/kvm/x86.c:9913:15: sparse:    struct kvm_pmu_event_filter *
   arch/x86/kvm/x86.c:1512:14: sparse: sparse: Expected constant expression in case statement
   arch/x86/kvm/x86.c:1512:35: sparse: sparse: Expected constant expression in case statement
   arch/x86/kvm/x86.c:1513:14: sparse: sparse: Expected constant expression in case statement
   arch/x86/kvm/x86.c:1514:14: sparse: sparse: Expected constant expression in case statement
   arch/x86/kvm/x86.c:1515:14: sparse: sparse: Expected constant expression in case statement

vim +/case +1512 arch/x86/kvm/x86.c

  1475	
  1476	/*
  1477	 * Write @data into the MSR specified by @index.  Select MSR specific fault
  1478	 * checks are bypassed if @host_initiated is %true.
  1479	 * Returns 0 on success, non-0 otherwise.
  1480	 * Assumes vcpu_load() was already called.
  1481	 */
  1482	static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
  1483				 bool host_initiated)
  1484	{
  1485		struct msr_data msr;
  1486	
  1487		switch (index) {
  1488		case MSR_FS_BASE:
  1489		case MSR_GS_BASE:
  1490		case MSR_KERNEL_GS_BASE:
  1491		case MSR_CSTAR:
  1492		case MSR_LSTAR:
  1493			if (is_noncanonical_address(data, vcpu))
  1494				return 1;
  1495			break;
  1496		case MSR_IA32_SYSENTER_EIP:
  1497		case MSR_IA32_SYSENTER_ESP:
  1498			/*
  1499			 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
  1500			 * non-canonical address is written on Intel but not on
  1501			 * AMD (which ignores the top 32-bits, because it does
  1502			 * not implement 64-bit SYSENTER).
  1503			 *
  1504			 * 64-bit code should hence be able to write a non-canonical
  1505			 * value on AMD.  Making the address canonical ensures that
  1506			 * vmentry does not fail on Intel after writing a non-canonical
  1507			 * value, and that something deterministic happens if the guest
  1508			 * invokes 64-bit SYSENTER.
  1509			 */
  1510			data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
  1511			break;
> 1512		case MSR_IA32_PL0_SSP ... MSR_IA32_PL3_SSP:
  1513		case MSR_IA32_U_CET:
  1514		case MSR_IA32_S_CET:
  1515		case MSR_IA32_INT_SSP_TAB:
  1516			if (is_noncanonical_address(data, vcpu))
  1517				return 1;
  1518		}
  1519	
  1520		msr.data = data;
  1521		msr.index = index;
  1522		msr.host_initiated = host_initiated;
  1523	
  1524		return kvm_x86_ops->set_msr(vcpu, &msr);
  1525	}
  1526	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

  parent reply	other threads:[~2020-03-20 15:48 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-20  3:43 [PATCH v10 0/8] Introduce support for guest CET feature Yang Weijiang
2020-03-20  3:43 ` [PATCH v10 1/8] KVM: VMX: Introduce CET VMX fields and flags Yang Weijiang
2020-03-20  3:43 ` [PATCH v10 2/8] KVM: VMX: Set up guest CET MSRs per KVM and host configuration Yang Weijiang
2020-03-20  3:43 ` [PATCH v10 3/8] KVM: VMX: Load CET states on vmentry/vmexit Yang Weijiang
2020-03-20 10:13   ` kbuild test robot
2020-03-20 11:22   ` kbuild test robot
2020-03-20  3:43 ` [PATCH v10 4/8] KVM: X86: Refresh CPUID on guest XSS change Yang Weijiang
2020-03-20 11:02   ` kbuild test robot
2020-03-20  3:43 ` [PATCH v10 5/8] KVM: X86: Load guest fpu state when accessing MSRs managed by XSAVES Yang Weijiang
2020-03-20  3:43 ` [PATCH v10 6/8] KVM: X86: Add userspace access interface for CET MSRs Yang Weijiang
2020-03-20 10:14   ` kbuild test robot
2020-03-20 15:48   ` kbuild test robot [this message]
2020-03-20  3:43 ` [PATCH v10 7/8] KVM: VMX: Enable CET support for nested VM Yang Weijiang
2020-03-20 11:02   ` kbuild test robot
2020-03-20  3:43 ` [PATCH v10 8/8] KVM: X86: Set CET feature bits for CPUID enumeration Yang Weijiang
2020-03-20 17:18   ` kbuild test robot
2020-03-20  3:43 ` [kvm-unit-tests PATCH] x86: Add tests for user-mode CET Yang Weijiang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=202003202309.SvJfslTC%lkp@intel.com \
    --to=lkp@intel.com \
    --cc=jmattson@google.com \
    --cc=kbuild-all@lists.01.org \
    --cc=kvm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=pbonzini@redhat.com \
    --cc=sean.j.christopherson@intel.com \
    --cc=weijiang.yang@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

Powered by JetHome