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Peter Anvin" , Jiri Olsa , Mark Rutland , Michael Petlan , Namhyung Kim , LKML , x86 Subject: [PATCH] perf/amd/uncore: Set all slices and threads to restore perf stat -a behaviour Date: Mon, 23 Mar 2020 18:31:59 -0500 Message-Id: <20200323233159.19601-1-kim.phillips@amd.com> X-Mailer: git-send-email 2.20.1 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: BN6PR11CA0016.namprd11.prod.outlook.com (2603:10b6:405:2::26) To SN6PR12MB2845.namprd12.prod.outlook.com (2603:10b6:805:75::33) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from amdsos-demo.kimphillips.home (165.204.84.11) by BN6PR11CA0016.namprd11.prod.outlook.com (2603:10b6:405:2::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2835.19 via Frontend Transport; Mon, 23 Mar 2020 23:32:09 +0000 X-Mailer: git-send-email 2.20.1 X-Originating-IP: [165.204.84.11] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 28bc6f60-1aa3-4e67-1fe7-08d7cf826916 X-MS-TrafficTypeDiagnostic: SN6PR12MB2718:|SN6PR12MB2718: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:655; X-Forefront-PRVS: 0351D213B3 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(4636009)(39850400004)(376002)(346002)(396003)(366004)(136003)(81166006)(2906002)(6486002)(316002)(8936002)(81156014)(66556008)(6512007)(478600001)(66476007)(66946007)(5660300002)(16526019)(26005)(6666004)(186003)(7416002)(44832011)(86362001)(956004)(2616005)(36756003)(52116002)(54906003)(7049001)(4326008)(8676002)(6506007)(110136005)(1076003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2718;H:SN6PR12MB2845.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bDd9tMB6RcPMV/22r5apSOeWE+KZ2RjhKf4pZJGf+iTjYWekQ5tZ5Y1VkY3qnPRwu2vMjx2M0idP1N0LEtynJVQUWiblpIdlrhwaETVapqXkpAxr+R6obAv73c3j7tkQ3Jb/pd/tzKArDF13swFAcP91r80g324nR+7gMZPszQ2bwiob74WjC669pGchy/wayS3LendwfjgBO0wgtEfcUcizGk0y8p4oYWYLsQoUyI1sVfZILOOFTYeooCrvVg4f8+3ZFKhpjlFOfzuA5T/StLY2SrdzkXRKWP16GODqQYaxYUud3CbHPFQ4Dj2nwHZKbDTJl9J//kh+YMUsUNR//zDUmtgJjwlL/Rwnl3txZXxegH2GPV3/mfeOYSebDcppvl16ThEdW4N5TiAFgbfiLEDwxfuXSFhf48qPwjTAEMYGIKThYRYKp1b5d7aGdvhB X-MS-Exchange-AntiSpam-MessageData: kX/XsMNgJol779mccvnMSkUHRKpcSMOiP+q5wdAzcNpKZczWw4w8gBMeobG/gby7A79kdLiJ9S5A36sdzSd46g6+m5xIseiGWWOUTObw1Xw1Y3VXPEtq754pjZGHQ3tNfQ0IfXMBWTqj5SDDMA3Lgg== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 28bc6f60-1aa3-4e67-1fe7-08d7cf826916 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2020 23:32:11.4928 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: m4SAY4r9AGeDC9/tVjTiLqrh8QY5wjjUZ2ZypEGM5cIcPIiZ5z8JVENMqVwVlUU6onQCCUXywQt3vRJZcIeKhQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2718 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit 2f217d58a8a0 ("perf/x86/amd/uncore: Set the thread mask for F17h L3 PMCs") inadvertently changed the uncore driver's behaviour wrt perf tool invocations with or without a CPU list, specified with -C / --cpu=. Change the behaviour of the driver to assume the former all-cpu (-a) case, which is the more commonly desired default. This fixes '-a -A' invocations without explicit cpu lists (-C) to not count L3 events only on behalf of the first thread of the first core in the L3 domain. BEFORE: Activity performed by the first thread of the last core (CPU#43) in CPU#40's L3 domain is not reported by CPU#40: sudo perf stat -a -A -e l3_request_g1.caching_l3_cache_accesses taskset -c 43 perf bench mem memcpy -s 32mb -l 100 -f default ... CPU36 21,835 l3_request_g1.caching_l3_cache_accesses CPU40 87,066 l3_request_g1.caching_l3_cache_accesses CPU44 17,360 l3_request_g1.caching_l3_cache_accesses ... AFTER: The L3 domain activity is now reported by CPU#40: sudo perf stat -a -A -e l3_request_g1.caching_l3_cache_accesses taskset -c 43 perf bench mem memcpy -s 32mb -l 100 -f default ... CPU36 354,891 l3_request_g1.caching_l3_cache_accesses CPU40 1,780,870 l3_request_g1.caching_l3_cache_accesses CPU44 315,062 l3_request_g1.caching_l3_cache_accesses ... Signed-off-by: Kim Phillips Fixes: 2f217d58a8a0 ("perf/x86/amd/uncore: Set the thread mask for F17h L3 PMCs") Cc: Stephane Eranian Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Ingo Molnar Cc: Thomas Gleixner Cc: Borislav Petkov Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: "H. Peter Anvin" Cc: Jiri Olsa Cc: Mark Rutland Cc: Michael Petlan Cc: Namhyung Kim Cc: LKML Cc: x86 --- Stephane, if you want to replace this with the manual thread specification patch you have, that's fine with me. arch/x86/events/amd/uncore.c | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index 76400c052b0e..e7e61c8b56bd 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -181,28 +181,16 @@ static void amd_uncore_del(struct perf_event *event, int flags) } /* - * Convert logical CPU number to L3 PMC Config ThreadMask format + * Return a full thread and slice mask until per-CPU is + * properly supported. */ -static u64 l3_thread_slice_mask(int cpu) +static u64 l3_thread_slice_mask(void) { - u64 thread_mask, core = topology_core_id(cpu); - unsigned int shift, thread = 0; + if (boot_cpu_data.x86 <= 0x18) + return AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK; - if (topology_smt_supported() && !topology_is_primary_thread(cpu)) - thread = 1; - - if (boot_cpu_data.x86 <= 0x18) { - shift = AMD64_L3_THREAD_SHIFT + 2 * (core % 4) + thread; - thread_mask = BIT_ULL(shift); - - return AMD64_L3_SLICE_MASK | thread_mask; - } - - core = (core << AMD64_L3_COREID_SHIFT) & AMD64_L3_COREID_MASK; - shift = AMD64_L3_THREAD_SHIFT + thread; - thread_mask = BIT_ULL(shift); - - return AMD64_L3_EN_ALL_SLICES | core | thread_mask; + return AMD64_L3_EN_ALL_SLICES | AMD64_L3_EN_ALL_CORES | + AMD64_L3_F19H_THREAD_MASK; } static int amd_uncore_event_init(struct perf_event *event) @@ -232,7 +220,7 @@ static int amd_uncore_event_init(struct perf_event *event) * For other events, the two fields do not affect the count. */ if (l3_mask && is_llc_event(event)) - hwc->config |= l3_thread_slice_mask(event->cpu); + hwc->config |= l3_thread_slice_mask(); uncore = event_to_amd_uncore(event); if (!uncore) -- 2.20.1