[PATCH] riscv: mm: synchronize MMU after page table update

[Nick Hu <nickhu@andestech.com>]

Similar to commit bf587caae305 ("riscv: mm: synchronize MMU after pte change")

For those riscv implementations whose TLB cannot synchronize with dcache,
an SFENCE.VMA is necessary after page table update.
This patch fixed two functions:

1. pgd_alloc
During fork, a parent process prepares pgd for its child and updates satp
later, but they may not run on the same core. Adding a remote SFENCE.VMA to
invalidate TLB in other cores is needed. Thus use flush_tlb_all() instead
of local_flush_tlb_all() here.
Similar approaches can be found in arm and csky.

2. __set_fixmap
Add a SFENCE.VMA after fixmap pte update.
Similar approaches can be found in arm and sh.

Signed-off-by: Nick Hu <nickhu@andestech.com>
Signed-off-by: Nylon Chen <nylon7@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
---
 arch/riscv/include/asm/pgalloc.h | 1 +
 arch/riscv/mm/init.c             | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/pgalloc.h b/arch/riscv/include/asm/pgalloc.h
index 3f601ee8233f..071468fa14b7 100644
--- a/arch/riscv/include/asm/pgalloc.h
+++ b/arch/riscv/include/asm/pgalloc.h
@@ -51,6 +51,7 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 		memcpy(pgd + USER_PTRS_PER_PGD,
 			init_mm.pgd + USER_PTRS_PER_PGD,
 			(PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+		flush_tlb_all();
 	}
 	return pgd;
 }
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index fab855963c73..a7f329503ed0 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -203,8 +203,8 @@ void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
 		set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
 	} else {
 		pte_clear(&init_mm, addr, ptep);
-		local_flush_tlb_page(addr);
 	}
+	local_flush_tlb_page(addr);
 }
 
 static pte_t *__init get_pte_virt(phys_addr_t pa)
-- 
2.17.0