From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6C70C54FCE for ; Tue, 24 Mar 2020 13:46:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BF83C2076E for ; Tue, 24 Mar 2020 13:46:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728022AbgCXNqT (ORCPT ); Tue, 24 Mar 2020 09:46:19 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:12121 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727398AbgCXNqT (ORCPT ); Tue, 24 Mar 2020 09:46:19 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 40A58CD4E978E9934518; Tue, 24 Mar 2020 21:46:06 +0800 (CST) Received: from DESKTOP-KKJBAGG.china.huawei.com (10.173.220.25) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Tue, 24 Mar 2020 21:45:59 +0800 From: Zhenyu Ye To: , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [RFC PATCH v4 0/6] arm64: tlb: add support for TTL feature Date: Tue, 24 Mar 2020 21:45:28 +0800 Message-ID: <20200324134534.1570-1-yezhenyu2@huawei.com> X-Mailer: git-send-email 2.22.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.173.220.25] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL feature allows TLBs to be issued with a level allowing for quicker invalidation. This series provide support for this feature. Patch 1 and Patch 2 was provided by Marc on his NV series[1] patches, which detect the TTL feature and add __tlbi_level interface. See patches for details, Thanks. [1] https://lore.kernel.org/linux-arm-kernel/20200211174938.27809-1-maz@kernel.org/ ChangeList: v1: add support for TTL feature in arm64. v2: build the patch on Marc's NV series[1]. v3: use vma->vm_flags to replace mm->context.flags. v4: add Marc's patches into my series. Marc Zyngier (2): arm64: Detect the ARMv8.4 TTL feature arm64: Add level-hinted TLB invalidation helper Zhenyu Ye (4): arm64: Add level-hinted TLB invalidation helper to tlbi_user mm: Add page table level flags to vm_flags arm64: tlb: Use translation level hint in vm_flags mm: Set VM_LEVEL flags in some tlb_flush functions arch/arm64/include/asm/cpucaps.h | 3 +- arch/arm64/include/asm/mmu.h | 2 + arch/arm64/include/asm/sysreg.h | 1 + arch/arm64/include/asm/tlb.h | 12 +++++ arch/arm64/include/asm/tlbflush.h | 74 ++++++++++++++++++++++++++++--- arch/arm64/kernel/cpufeature.c | 11 +++++ arch/arm64/mm/hugetlbpage.c | 4 +- arch/arm64/mm/mmu.c | 14 ++++++ include/asm-generic/pgtable.h | 16 ++++++- include/linux/mm.h | 10 +++++ include/trace/events/mmflags.h | 15 ++++++- mm/huge_memory.c | 8 +++- 12 files changed, 157 insertions(+), 13 deletions(-) -- 2.19.1