From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5EF3C54FD1 for ; Tue, 24 Mar 2020 14:20:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9FBC120789 for ; Tue, 24 Mar 2020 14:20:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="j1P7KuTV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727551AbgCXOUi (ORCPT ); Tue, 24 Mar 2020 10:20:38 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:51584 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728198AbgCXOUe (ORCPT ); Tue, 24 Mar 2020 10:20:34 -0400 Received: by mail-wm1-f68.google.com with SMTP id c187so3392059wme.1 for ; Tue, 24 Mar 2020 07:20:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pMoqaL6yn4wVYVlvTr5RoruqY0oplnpZZkK4h3Bk1Vc=; b=j1P7KuTVSjxrPEtajniTPWPfAOlurldgsF/xktOKR/xrk7/1/NQs15p+Wh7faGwx5J 31rujTLqTWRQMqH3/Qe4/2GOhv1LyhS6h3aQmndYeiWEtihu+gMRLJ8Mhsc4Atutwenr P5yimGaHugk71bQO+JmtIQ7GkIpIRgbfPi0L04cCM3jPUZ8Yg6RBzuOGm+sOD+wR9+90 hG1wSKJEIKqlV5EB1NyWZFEzvJXJGDqbt4fg81lUn6ckvIHasxInI05zYHRS0tL/A6kF wHF7icX/QfK7X5YWY18rNDRgIKKk1LgiCm6vJjVPQiHDPsc7B2m0Uhv6VF7NQFKGCV42 hC2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pMoqaL6yn4wVYVlvTr5RoruqY0oplnpZZkK4h3Bk1Vc=; b=tVy/gbbcPKy5zQQAHbgjM9xA0k20TOhSevj27kgL+TxLMQC7qx9+rl01SCN5wurvVO p0oUxrSJe7kpfRtUhXVuT7qBcZaNlzf9Oub4AOzr9LpGqLFwQ6mIUH0sRa7D3wurGbg6 j1dAQdDYbnCQS2iHn0KvPuG7CuLZsDAIkxyXKk8ZL4TxDpzMSy2D0Zc42uvkvybyZk+q JXDs4sNrzb5n64JEg8zq7v92qKLFVF3nmlYO/Qu8DFi4ParISJ72eMdqG+/hpiKm6/oR yK9f1rAb3dXPWH6K/rgDwoQRAC90CI4RZiZs8QaR2Xuh8LRxg8dsGMvF40/WFpuLRmqs zFqQ== X-Gm-Message-State: ANhLgQ2tJvykdhC4Ngm8m1/OQfwaXwH/ShPZP6DT53ECIn/v81XsxHei sgiPi/7u7zSNL9zTS2QZYkfxdA== X-Google-Smtp-Source: ADFU+vtdVs9Y/Tzl2+XQY7ViTUqyXqgfFO/2wOmSWtCEH4wZVZeKpxYXjUZe5vF6CoRkmPuskQbK2Q== X-Received: by 2002:a1c:6605:: with SMTP id a5mr5962156wmc.32.1585059632470; Tue, 24 Mar 2020 07:20:32 -0700 (PDT) Received: from bender.baylibre.local ([2a01:e35:2ec0:82b0:5c5f:613e:f775:b6a2]) by smtp.gmail.com with ESMTPSA id o4sm28688472wrp.84.2020.03.24.07.20.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2020 07:20:32 -0700 (PDT) From: Neil Armstrong To: daniel@ffwll.ch, dri-devel@lists.freedesktop.org Cc: ppaalanen@gmail.com, mjourdan@baylibre.com, brian.starkey@arm.com, Neil Armstrong , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 7/7] drm/meson: overlay: setup overlay for Amlogic FBC Scatter Memory layout Date: Tue, 24 Mar 2020 15:20:16 +0100 Message-Id: <20200324142016.31824-8-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200324142016.31824-1-narmstrong@baylibre.com> References: <20200324142016.31824-1-narmstrong@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Setup the Amlogic FBC decoder for the VD1 video overlay plane to use read the FBC header as Scatter Memory layout reference. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_overlay.c | 48 +++++++++++++++++---------- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_overlay.c b/drivers/gpu/drm/meson/meson_overlay.c index 8b9d4984b2a7..af4698ae5281 100644 --- a/drivers/gpu/drm/meson/meson_overlay.c +++ b/drivers/gpu/drm/meson/meson_overlay.c @@ -487,6 +487,9 @@ static void meson_overlay_atomic_update(struct drm_plane *plane, AFBC_HOLD_LINE_NUM(8) | AFBC_BURST_LEN(2); + if (fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC_SCATTER) + priv->viu.vd1_afbc_mode |= AFBC_SCATTER_MODE; + if (fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC_MEM_SAVING) priv->viu.vd1_afbc_mode |= AFBC_BLK_MEM_MODE; @@ -675,23 +678,32 @@ static void meson_overlay_atomic_update(struct drm_plane *plane, } if (priv->viu.vd1_afbc) { - /* Default mode is 4k per superblock */ - unsigned long block_size = 4096; - unsigned long body_size; - - /* 8bit mem saving mode is 3072bytes per superblock */ - if (priv->viu.vd1_afbc_mode & AFBC_BLK_MEM_MODE) - block_size = 3072; - - body_size = (ALIGN(priv->viu.vd1_stride0, 64) / 64) * - (ALIGN(priv->viu.vd1_height0, 32) / 32) * - block_size; - - priv->viu.vd1_afbc_body_addr = priv->viu.vd1_addr0 >> 4; - - /* Header is after body content */ - priv->viu.vd1_afbc_head_addr = (priv->viu.vd1_addr0 + - body_size) >> 4; + if (priv->viu.vd1_afbc_mode & AFBC_SCATTER_MODE) { + /* + * In Scatter mode, the header contains the physical + * body content layout, thus the body content + * size isn't needed. + */ + priv->viu.vd1_afbc_head_addr = priv->viu.vd1_addr0 >> 4; + priv->viu.vd1_afbc_body_addr = 0; + } else { + /* Default mode is 4k per superblock */ + unsigned long block_size = 4096; + unsigned long body_size; + + /* 8bit mem saving mode is 3072bytes per superblock */ + if (priv->viu.vd1_afbc_mode & AFBC_BLK_MEM_MODE) + block_size = 3072; + + body_size = (ALIGN(priv->viu.vd1_stride0, 64) / 64) * + (ALIGN(priv->viu.vd1_height0, 32) / 32) * + block_size; + + priv->viu.vd1_afbc_body_addr = priv->viu.vd1_addr0 >> 4; + /* Header is after body content */ + priv->viu.vd1_afbc_head_addr = (priv->viu.vd1_addr0 + + body_size) >> 4; + } } priv->viu.vd1_enabled = true; @@ -771,6 +783,8 @@ static const uint32_t supported_drm_formats[] = { }; static const uint64_t format_modifiers[] = { + DRM_FORMAT_MOD_AMLOGIC_FBC(DRM_FORMAT_MOD_AMLOGIC_FBC_LAYOUT_SCATTER | + DRM_FORMAT_MOD_AMLOGIC_FBC_MEM_SAVING), DRM_FORMAT_MOD_AMLOGIC_FBC(DRM_FORMAT_MOD_AMLOGIC_FBC_LAYOUT_BASIC | DRM_FORMAT_MOD_AMLOGIC_FBC_MEM_SAVING), DRM_FORMAT_MOD_AMLOGIC_FBC(DRM_FORMAT_MOD_AMLOGIC_FBC_LAYOUT_BASIC), -- 2.22.0