From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16A61C2BB55 for ; Thu, 9 Apr 2020 11:36:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DF1AA20A8B for ; Thu, 9 Apr 2020 11:35:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="dr34AMpJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726598AbgDILf6 (ORCPT ); Thu, 9 Apr 2020 07:35:58 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:45224 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726502AbgDILf5 (ORCPT ); Thu, 9 Apr 2020 07:35:57 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1586432157; h=Content-Transfer-Encoding: MIME-Version: Message-Id: Date: Subject: Cc: To: From: Sender; bh=2nl8GwNziueLzCqZ1teRBsn+iOEVqe/mARGJerFZsdI=; b=dr34AMpJ0W5nb/rouSQ087Xwy5CPOaZaOGfasR4d2qdsQXjmunRknjxyIC0QmBdcLYNqwhdy RCWYsfPKpnLQ33el0Rs5j0NAMyLWfJukJTJqz+sLCZev8wzb8DnbJi6RCNXzAMbFc1MhvpVt fXtvP2yS4MMg8hKwT9Plx5aS2xk= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e8f0898.7f02fd849ca8-smtp-out-n02; Thu, 09 Apr 2020 11:35:52 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id AA208C432C2; Thu, 9 Apr 2020 11:35:52 +0000 (UTC) Received: from blr-ubuntu-311.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 37867C433CB; Thu, 9 Apr 2020 11:35:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 37867C433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=saiprakash.ranjan@codeaurora.org From: Sai Prakash Ranjan To: Mathieu Poirier , Suzuki K Poulose , mike.leach@linaro.org, Stephen Boyd Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Sai Prakash Ranjan Subject: [PATCH] coresight: tmc: Read TMC mode only when TMC hw is enabled Date: Thu, 9 Apr 2020 17:05:38 +0530 Message-Id: <20200409113538.5008-1-saiprakash.ranjan@codeaurora.org> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Reading TMC mode register in tmc_read_prepare_etb without enabling the TMC hardware leads to async exceptions like the one in the call trace below. This can happen if the user tries to read the TMC etf data via device node without setting up source and the sink first which enables the TMC hardware in the path. So make sure that the TMC is enabled before we try to read TMC data. Kernel panic - not syncing: Asynchronous SError Interrupt CPU: 7 PID: 2605 Comm: hexdump Tainted: G S 5.4.30 #122 Call trace: dump_backtrace+0x0/0x188 show_stack+0x20/0x2c dump_stack+0xdc/0x144 panic+0x168/0x36c panic+0x0/0x36c arm64_serror_panic+0x78/0x84 do_serror+0x130/0x138 el1_error+0x84/0xf8 tmc_read_prepare_etb+0x88/0xb8 tmc_open+0x40/0xd8 misc_open+0x120/0x158 chrdev_open+0xb8/0x1a4 do_dentry_open+0x268/0x3a0 vfs_open+0x34/0x40 path_openat+0x39c/0xdf4 do_filp_open+0x90/0x10c do_sys_open+0x150/0x3e8 __arm64_compat_sys_openat+0x28/0x34 el0_svc_common+0xa8/0x160 el0_svc_compat_handler+0x2c/0x38 el0_svc_compat+0x8/0x10 Fixes: 4525412a5046 ("coresight: tmc: making prepare/unprepare functions generic") Reported-by: Stephen Boyd Signed-off-by: Sai Prakash Ranjan --- drivers/hwtracing/coresight/coresight-tmc.c | 5 +++++ drivers/hwtracing/coresight/coresight-tmc.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 1cf82fa58289..7bae69748ab7 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -62,11 +62,13 @@ void tmc_flush_and_stop(struct tmc_drvdata *drvdata) void tmc_enable_hw(struct tmc_drvdata *drvdata) { + drvdata->enable = true; writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL); } void tmc_disable_hw(struct tmc_drvdata *drvdata) { + drvdata->enable = false; writel_relaxed(0x0, drvdata->base + TMC_CTL); } @@ -102,6 +104,9 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdata) { int ret = 0; + if (!drvdata->enable) + return -EINVAL; + switch (drvdata->config_type) { case TMC_CONFIG_TYPE_ETB: case TMC_CONFIG_TYPE_ETF: diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 71de978575f3..7c8712a6ed8d 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -191,6 +191,7 @@ struct tmc_drvdata { struct miscdevice miscdev; spinlock_t spinlock; pid_t pid; + bool enable; bool reading; union { char *buf; /* TMC ETB */ -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation