From: Charles Keepax <ckeepax@opensource.cirrus.com>
To: Shengjiu Wang <shengjiu.wang@nxp.com>
Cc: <lgirdwood@gmail.com>, <broonie@kernel.org>, <perex@perex.cz>,
<tiwai@suse.com>, <tglx@linutronix.de>, <allison@lohutok.net>,
<info@metux.net>, <patches@opensource.cirrus.com>,
<alsa-devel@alsa-project.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] ASoC: wm8962: set CLOCKING2 as non-volatile register
Date: Fri, 24 Apr 2020 08:47:54 +0000 [thread overview]
Message-ID: <20200424084754.GI44490@ediswmail.ad.cirrus.com> (raw)
In-Reply-To: <6d25d5b36d4b9aeb8655b5e947dad52214e34177.1587693523.git.shengjiu.wang@nxp.com>
On Fri, Apr 24, 2020 at 10:01:38AM +0800, Shengjiu Wang wrote:
> Previously CLOCKING2 is set as a volatile register, but cause
> issue at suspend & resume, that some bits of CLOCKING2 is not
> restored at resume, for example SYSCLK_SRC bits, then the output
> clock is wrong.
>
> The volatile property is caused by CLASSD_CLK_DIV bits,
> which are controlled by the chip itself. But the datasheet
> claims these are read only and protected by the security key,
> and they are not read by the driver at all.
>
> So it should be safe to change CLOCKING2 to be non-volatile.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> ---
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Thanks,
Charles
next prev parent reply other threads:[~2020-04-24 8:49 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-24 2:01 Shengjiu Wang
2020-04-24 8:47 ` Charles Keepax [this message]
2020-04-24 10:31 ` Mark Brown
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