From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16355C4724C for ; Wed, 6 May 2020 06:14:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E973220714 for ; Wed, 6 May 2020 06:14:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727945AbgEFGOn (ORCPT ); Wed, 6 May 2020 02:14:43 -0400 Received: from mga11.intel.com ([192.55.52.93]:13733 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726495AbgEFGOm (ORCPT ); Wed, 6 May 2020 02:14:42 -0400 IronPort-SDR: Aea8bJ0TPKSGcD2+YdR056vVwmezCMYnZNc80YCGOkgY80P0/ClkoH5fuIy38WYW8/isyxkgmZ WLdX2Fwf4M4g== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2020 23:14:42 -0700 IronPort-SDR: 8SU0ZqGeDxAqRO3wxKhezSMu6O2lsRivPI+hZNxm7YSA4YXKFMebS7DjQxzKlx6yRlYm9rM62J 4aPiWNDugCFA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,358,1583222400"; d="scan'208";a="369691803" Received: from lahna.fi.intel.com (HELO lahna) ([10.237.72.163]) by fmsmga001.fm.intel.com with SMTP; 05 May 2020 23:14:39 -0700 Received: by lahna (sSMTP sendmail emulation); Wed, 06 May 2020 09:14:38 +0300 Date: Wed, 6 May 2020 09:14:38 +0300 From: Mika Westerberg To: Kai-Heng Feng Cc: bhelgaas@google.com, Heiner Kallweit , "Rafael J. Wysocki" , Keith Busch , Chris Packham , Yicong Yang , Krzysztof Wilczynski , "open list:PCI SUBSYSTEM" , open list Subject: Re: [PATCH v3] PCI/ASPM: Enable ASPM for bridge-to-bridge link Message-ID: <20200506061438.GR487496@lahna.fi.intel.com> References: <20200505122801.12903-1-kai.heng.feng@canonical.com> <20200505173423.26968-1-kai.heng.feng@canonical.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200505173423.26968-1-kai.heng.feng@canonical.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 06, 2020 at 01:34:21AM +0800, Kai-Heng Feng wrote: > The TI PCIe-to-PCI bridge prevents the Intel SoC from entering power > state deeper than PC3 due to disabled ASPM, consumes lots of unnecessary > power. On Windows ASPM L1 is enabled on the device and its upstream > bridge, so it can make the Intel SoC reach PC8 or PC10 to save lots of > power. > > In short, ASPM always gets disabled on bridge-to-bridge link. Excelent finding :) I've heard several reports complaining that we can't enter PC10 when TBT is enabled and I guess this explains it. > The special case was part of first ASPM introduction patch, commit > 7d715a6c1ae5 ("PCI: add PCI Express ASPM support"). However, it didn't > explain why ASPM needs to be disabled in special bridge-to-bridge case. > > Let's remove the the special case, as PCIe spec already envisioned ASPM > on bridge-to-bridge link. > > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=207571 > Signed-off-by: Kai-Heng Feng Reviewed-by: Mika Westerberg