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[86.9.19.6]) by smtp.gmail.com with ESMTPSA id c190sm3591094wme.10.2020.05.06.08.06.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2020 08:06:11 -0700 (PDT) Date: Wed, 6 May 2020 16:06:09 +0100 From: Daniel Thompson To: Will Deacon Cc: Catalin Marinas , Douglas Anderson , Jason Wessel , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, patches@linaro.org Subject: Re: [PATCH v2] arm64: cacheflush: Fix KGDB trap detection Message-ID: <20200506150609.kya3nygfvdwvimad@holly.lan> References: <20200504170518.2959478-1-daniel.thompson@linaro.org> <20200504204803.GA5657@willie-the-truck> <20200505141529.2qb35fbqudtac3ys@holly.lan> <20200505150916.GC24239@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200505150916.GC24239@willie-the-truck> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 05, 2020 at 04:09:16PM +0100, Will Deacon wrote: > On Tue, May 05, 2020 at 03:15:29PM +0100, Daniel Thompson wrote: > > On Mon, May 04, 2020 at 09:48:04PM +0100, Will Deacon wrote: > > > On Mon, May 04, 2020 at 06:05:18PM +0100, Daniel Thompson wrote: > > > > diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h > > > > index e6cca3d4acf7..ce50c1f1f1ea 100644 > > > > --- a/arch/arm64/include/asm/cacheflush.h > > > > +++ b/arch/arm64/include/asm/cacheflush.h > > > > @@ -79,7 +79,7 @@ static inline void flush_icache_range(unsigned long start, unsigned long end) > > > > * IPI all online CPUs so that they undergo a context synchronization > > > > * event and are forced to refetch the new instructions. > > > > */ > > > > -#ifdef CONFIG_KGDB > > > > + > > > > /* > > > > * KGDB performs cache maintenance with interrupts disabled, so we > > > > * will deadlock trying to IPI the secondary CPUs. In theory, we can > > > > @@ -89,9 +89,9 @@ static inline void flush_icache_range(unsigned long start, unsigned long end) > > > > * the patching operation, so we don't need extra IPIs here anyway. > > > > * In which case, add a KGDB-specific bodge and return early. > > > > */ > > > > - if (kgdb_connected && irqs_disabled()) > > > > + if (in_dbg_master()) > > > > > > Does this imply that irqs are disabled? > > > > Yes. Except for bugs... > > > > Assuming CONFIG_KGDB is enabled then in_dbg_master() expands to: > > > > (raw_smp_processor_id() == atomic_read(&kgdb_active)) > > Aha, so this can drop the raw_ prefix and call smp_processor_id() instead? We need to allow in_dbg_master() to be called from preemptible contexts (because its job it to disclose information about our executions context) but given irqs are always disabled when we in_dbg_master() then I think we can make this and rely on short-circuit eval to avoid PREEMPT_DEBUG errors: (irqs_disabled() && (smp_processor_id() == atomic_read(&kgdb_active))) > I can queue the arm64 patch regardless. I don't want to hide anything... when I looked closer I realized that the above change also eliminates a small window where the original macro can spuriously evaluate to true. Specifically if we migrate to a new core after reading the processor id and the previous core takes a breakpoint then we would evaluate true if we read kgdb_active before we get the IPI to bring us to halt. Sorry for overlooking this in my reply yesterday! I'll have a patch out for this shortly. Daniel.