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Mon, 18 May 2020 09:15:16 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Jason Cooper , Marc Zyngier Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , stable@vger.kernel.org Subject: [PATCH v2 1/3] irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map() Date: Mon, 18 May 2020 14:44:39 +0530 Message-Id: <20200518091441.94843-2-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200518091441.94843-1-anup.patel@wdc.com> References: <20200518091441.94843-1-anup.patel@wdc.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: MA1PR01CA0155.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::25) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (106.51.27.1) by MA1PR01CA0155.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3000.25 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: GUSLyCvxRIUJRYon7Pz6xCHLtWzEvVdSZmARAIQYMEA23/oXbZlHuBe8dKOFAkMZ1VizRTq6fyDokUM/GGoUqJ7Q2fimRZzzWcTumdZSemq9P+XaXlHXpa+ktwNVrsk/GhtkbzLzH78g+MVNBh9lVAbaEFgvXbC4PLCnzHbQovOX2XmfSvXlZs5/jRZ7BpFOeFICfvzZO0KnlieWZCgHsxPWg4/gRawcmDTOiFCH8UwRaLeepMAq2YhrvKSH3/RGXMD5TFKuY3gyhxNKRC52oiwYTP7zGiWzi8DVW6Whj4/Bsj9d8SYJzq4N8E1ZrdEk4L6LEC5LnSY4x8NiTAyWy0ff3QmYyADkIgqrRxs72X9LqGQeJfrcqNVAUTG5+7W8DrVU+vxHw1zBK/VPxtcTSFzRA7YD0JrSHxmQ9OYfw/Nci3eb19QqGawJj7RTXhWTpbMMHrx1hHW1VhGs5uo3CWhRLaZR1QKM43f/c4rMoas= X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3e5d2f3b-48c4-4fae-ab21-08d7fb0bfa6a X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2020 09:15:16.5178 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: yDa3eT6PUvQkvLLKFg1IJUfmAxKT2CEYJfYKTVUt+0kDClNWCtlkmaixwjSlVyDNeTLsPwlJH7EkmU/1es3clw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR04MB4155 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For multiple PLIC instances, each PLIC can only target a subset of CPUs which is represented by "lmask" in the "struct plic_priv". Currently, the default irq affinity for each PLIC interrupt is all online CPUs which is illegal value for default irq affinity when we have multiple PLIC instances. To fix this, we now set "lmask" as the default irq affinity in for each interrupt in plic_irqdomain_map(). Fixes: f1ad1133b18f ("irqchip/sifive-plic: Add support for multiple PLICs") Cc: stable@vger.kernel.org Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 822e074c0600..9f7f8ce88c00 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -176,9 +176,12 @@ static struct irq_chip plic_chip = { static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { + struct plic_priv *priv = d->host_data; + irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, handle_fasteoi_irq, NULL, NULL); irq_set_noprobe(irq); + irq_set_affinity(irq, &priv->lmask); return 0; } -- 2.25.1