From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.1 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A9BAC433E0 for ; Wed, 20 May 2020 01:53:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 67DE120708 for ; Wed, 20 May 2020 01:53:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="c8r8iiQk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728451AbgETBxm (ORCPT ); Tue, 19 May 2020 21:53:42 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:28039 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726595AbgETBxm (ORCPT ); Tue, 19 May 2020 21:53:42 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1589939620; h=In-Reply-To: Content-Type: MIME-Version: References: Message-ID: Subject: Cc: To: From: Date: Sender; bh=bipPZZl6i0uiVygGHlA0ONnrop/ReE+5AmOxNg/wCQ4=; b=c8r8iiQknM3boT2CDTE/QGy3J1yol/zi3PZlHycp3ZYLdWU9j7DiWG/uHzgLr4heks9W3Y9I G+OP95sheX5dwnqiK956UczzWn3RtipAUo0EWd3NcVf6RNgxF2cq+0PhX6/xTVkSt6xabGx+ Ln7HxO2IrNQk3bqIer+rNFegex0= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5ec48d9a.7fc66ff11928-smtp-out-n05; Wed, 20 May 2020 01:53:30 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id ECAC9C43387; Wed, 20 May 2020 01:53:29 +0000 (UTC) Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 681B1C433C6; Wed, 20 May 2020 01:53:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 681B1C433C6 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org Date: Tue, 19 May 2020 19:53:26 -0600 From: Jordan Crouse To: Will Deacon Cc: iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org, Joerg Roedel , linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 2/5] iommu/arm-smmu: Add support for TTBR1 Message-ID: <20200520015326.GA31730@jcrouse1-lnx.qualcomm.com> Mail-Followup-To: Will Deacon , iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org, Joerg Roedel , linux-kernel@vger.kernel.org References: <20200409233350.6343-1-jcrouse@codeaurora.org> <20200409233350.6343-3-jcrouse@codeaurora.org> <20200518145959.GK32394@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200518145959.GK32394@willie-the-truck> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 18, 2020 at 03:59:59PM +0100, Will Deacon wrote: > On Thu, Apr 09, 2020 at 05:33:47PM -0600, Jordan Crouse wrote: > > Add support to enable TTBR1 if the domain requests it via the > > DOMAIN_ATTR_SPLIT_TABLES attribute. If enabled by the hardware > > and pagetable configuration the driver will configure the TTBR1 region > > and program the domain pagetable on TTBR1. TTBR0 will be disabled. > > > > After attaching the device the value of he domain attribute can > > be queried to see if the split pagetables were successfully programmed. > > The domain geometry will be updated as well so that the caller can > > determine the active region for the pagetable that was programmed. > > > > Signed-off-by: Jordan Crouse > > --- > > > > drivers/iommu/arm-smmu.c | 48 ++++++++++++++++++++++++++++++++++------ > > drivers/iommu/arm-smmu.h | 24 +++++++++++++++----- > > 2 files changed, 59 insertions(+), 13 deletions(-) > > > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > > index a6a5796e9c41..db6d503c1673 100644 > > --- a/drivers/iommu/arm-smmu.c > > +++ b/drivers/iommu/arm-smmu.c > > @@ -555,11 +555,16 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, > > cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr; > > cb->ttbr[1] = 0; > > } else { > > - cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > > - cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, > > - cfg->asid); > > - cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, > > - cfg->asid); > > + cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, > > + cfg->asid); > > + > > + if (pgtbl_cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) { > > + cb->ttbr[1] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > > + } else { > > + cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > > + cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, > > + cfg->asid); > > + } > > This looks odd to me. As I mentioned before, the SMMU driver absolutely has > to manage the ASID space, so we should be setting it in both TTBRs here. Somebody had suggested a while back to only do TTBR0 but I agree that it makes more sense for it to be on both. > > diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h > > index 8d1cd54d82a6..5f6d0af7c8c8 100644 > > --- a/drivers/iommu/arm-smmu.h > > +++ b/drivers/iommu/arm-smmu.h > > @@ -172,6 +172,7 @@ enum arm_smmu_cbar_type { > > #define ARM_SMMU_TCR_SH0 GENMASK(13, 12) > > #define ARM_SMMU_TCR_ORGN0 GENMASK(11, 10) > > #define ARM_SMMU_TCR_IRGN0 GENMASK(9, 8) > > +#define ARM_SMMU_TCR_EPD0 BIT(7) > > #define ARM_SMMU_TCR_T0SZ GENMASK(5, 0) > > > > #define ARM_SMMU_VTCR_RES1 BIT(31) > > @@ -343,16 +344,27 @@ struct arm_smmu_domain { > > struct mutex init_mutex; /* Protects smmu pointer */ > > spinlock_t cb_lock; /* Serialises ATS1* ops and TLB syncs */ > > struct iommu_domain domain; > > + bool split_pagetables; > > }; > > > > static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg) > > { > > - return ARM_SMMU_TCR_EPD1 | > > - FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) | > > - FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) | > > - FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) | > > - FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) | > > - FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz); > > + u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) | > > + FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) | > > + FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) | > > + FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) | > > + FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz); > > + > > + /* > > + * When TTBR1 is selected shift the TCR fields by 16 bits and disable > > + * translation in TTBR0 > > + */ > > + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) > > + tcr = (tcr << 16) | ARM_SMMU_TCR_EPD0; > > This looks reasonably dodgy to me, as you copy a RESERVED bit into the A1 > field. Furthermore, for 32-bit context banks you've got the EAE bit to > contend with as well. I can swizzle it more if we need to. I think Robin's main objection was that we didn't want to construct the whole half of the TCR twice and have a bunch of field definitions for the T1 space that are only used in this special case. > Perhaps we shouldn't expose DOMAIN_ATTR_SPLIT_TABLES for anything other than > the 64-bit page table format. We kind of enforce that in arm_smmu_init_domain_context [1] by only allowing the quirk to be set when cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64 and stage 1. I'm not sure if that is formal enough or if we should bake something in to io-pgtable-arm to warn against it too. Jordan -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project