From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B0A5C433E1 for ; Fri, 22 May 2020 07:31:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 665202073B for ; Fri, 22 May 2020 07:31:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729006AbgEVHbZ (ORCPT ); Fri, 22 May 2020 03:31:25 -0400 Received: from elvis.franken.de ([193.175.24.41]:34188 "EHLO elvis.franken.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728369AbgEVHbL (ORCPT ); Fri, 22 May 2020 03:31:11 -0400 Received: from uucp (helo=alpha) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1jc28x-0003HE-01; Fri, 22 May 2020 09:30:59 +0200 Received: by alpha.franken.de (Postfix, from userid 1000) id B7A8EC015D; Fri, 22 May 2020 09:28:03 +0200 (CEST) Date: Fri, 22 May 2020 09:28:03 +0200 From: Thomas Bogendoerfer To: Serge Semin Cc: Serge Semin , Alexey Malahov , Paul Burton , Ralf Baechle , Arnd Bergmann , Rob Herring , devicetree@vger.kernel.org, Jiaxun Yang , Huacai Chen , Alexander Lobakin , Fangrui Song , Ard Biesheuvel , Nathan Chancellor , Cedric Hombourger , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 04/13] mips: Add MIPS Warrior P5600 support Message-ID: <20200522072803.GB7331@alpha.franken.de> References: <20200521140725.29571-1-Sergey.Semin@baikalelectronics.ru> <20200521140725.29571-5-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200521140725.29571-5-Sergey.Semin@baikalelectronics.ru> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 21, 2020 at 05:07:15PM +0300, Serge Semin wrote: > This is a MIPS32 Release 5 based IP core with XPA, EVA, dual/quad issue > exec pipes, MMU with two-levels TLB, UCA, MSA, MDU core level features > and system level features like up to six P5600 calculation cores, CM2 > with L2 cache, IOCU/IOMMU (though might be unused depending on the > system-specific IP core configuration), GIC, CPC, virtualisation module, > eJTAG and PDtrace. > > As being MIPS32 Release 5 based core it provides all the features > available by the CPU_MIPS32_R5 config, while adding a few more like > UCA attribute support, availability of CPU-freq (by means of L2/CM > clock ratio setting), EI/VI GIC modes detection at runtime. > > In addition to this if P5600 architecture is enabled modern GNU GCC > provides a specific tuning for P5600 processors with respect to the > classic MIPS32 Release 5. First of all branch-likely avoidance is > activated only when the code is compiled with the speed optimization > (avoidance is always enabled for the pure MIPS32 Release 5 > architecture). Secondly the madd/msub avoidance is enabled since > madd/msub utilization isn't profitable due to overhead of getting the > result out of the HI/LO registers. Multiply-accumulate instructions are > activated and utilized together with the necessary code reorder when > multiply-add/multiply-subtract statements are met. Finally load/store > bonding is activated by default. All of these optimizations may make > the code relatively faster than if just MIP32 release 5 architecture > was requested. > > Co-developed-by: Alexey Malahov > Signed-off-by: Alexey Malahov > Signed-off-by: Serge Semin > Cc: Thomas Bogendoerfer > Cc: Paul Burton > Cc: Ralf Baechle > Cc: Arnd Bergmann > Cc: Rob Herring > Cc: devicetree@vger.kernel.org > --- > arch/mips/Kconfig | 37 +++++++++++++++++++++++++++++----- > arch/mips/Makefile | 1 + > arch/mips/include/asm/module.h | 2 ++ > 3 files changed, 35 insertions(+), 5 deletions(-) applied to mips-next. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]