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[114.171.61.116]) by smtp.googlemail.com with ESMTPSA id f23sm2360703pja.8.2020.06.16.05.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 05:17:27 -0700 (PDT) From: Daniel Palmer To: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Palmer Subject: [PATCH v4 08/12] ARM: mstar: Add Armv7 base dtsi Date: Tue, 16 Jun 2020 21:15:21 +0900 Message-Id: <20200616121525.1409790-9-daniel@0x0f.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200616121525.1409790-1-daniel@0x0f.com> References: <20200612130032.3905240-2-daniel@0x0f.com> <20200616121525.1409790-1-daniel@0x0f.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adds initial dtsi for the base MStar/Sigmastar Armv7 SoCs. These SoCs have very similar memory maps and this will avoid duplicating nodes across multiple dtsis. Signed-off-by: Daniel Palmer --- MAINTAINERS | 1 + arch/arm/boot/dts/mstar-v7.dtsi | 83 +++++++++++++++++++++++++++++++++ 2 files changed, 84 insertions(+) create mode 100644 arch/arm/boot/dts/mstar-v7.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 3d31bc749f6d..54a2fc60a1d9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2123,6 +2123,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar.yaml +F: arch/arm/boot/dts/mstar-v7.dtsi F: arch/arm/mach-mstar/ ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi new file mode 100644 index 000000000000..3b99bb435bb5 --- /dev/null +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + }; + + arch_timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + /* + * we shouldn't need this but the vendor + * u-boot is broken + */ + clock-frequency = <6000000>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x16001000 0x16001000 0x00007000>, + <0x1f000000 0x1f000000 0x00400000>; + + gic: interrupt-controller@16001000 { + compatible = "arm,cortex-a7-gic"; + reg = <0x16001000 0x1000>, + <0x16002000 0x2000>, + <0x16004000 0x2000>, + <0x16006000 0x2000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + riu: bus@1f000000 { + compatible = "simple-bus"; + reg = <0x1f000000 0x00400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1f000000 0x00400000>; + + l3bridge: l3bridge@204400 { + compatible = "mstar,l3bridge"; + reg = <0x204400 0x200>; + }; + + pm_uart: uart@221000 { + compatible = "ns16550a"; + reg = <0x221000 0x100>; + reg-shift = <3>; + clock-frequency = <172000000>; + status = "disabled"; + }; + }; + }; +}; -- 2.27.0.rc0