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[156.34.48.30]) by smtp.gmail.com with ESMTPSA id f127sm210137qkb.55.2020.06.17.08.28.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Jun 2020 08:28:35 -0700 (PDT) Received: from jgg by mlx with local (Exim 4.93) (envelope-from ) id 1jlZzP-009d7z-9q; Wed, 17 Jun 2020 12:28:35 -0300 Date: Wed, 17 Jun 2020 12:28:35 -0300 From: Jason Gunthorpe To: Daniel Vetter Cc: Thomas =?utf-8?B?SGVsbHN0csO2bSAoSW50ZWwp?= , DRI Development , linux-rdma , Intel Graphics Development , Maarten Lankhorst , LKML , amd-gfx list , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Thomas Hellstrom , Daniel Vetter , "open list:DMA BUFFER SHARING FRAMEWORK" , Christian =?utf-8?B?S8O2bmln?= , Mika Kuoppala Subject: Re: [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations Message-ID: <20200617152835.GF6578@ziepe.ca> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-5-daniel.vetter@ffwll.ch> <20200611083430.GD20149@phenom.ffwll.local> <20200611141515.GW6578@ziepe.ca> <20200616120719.GL20149@phenom.ffwll.local> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jun 17, 2020 at 08:48:50AM +0200, Daniel Vetter wrote: > Now my understanding for rdma is that if you don't have hw page fault > support, The RDMA ODP feature is restartable HW page faulting just like nouveau has. The classical MR feature doesn't have this. Only mlx5 HW supports ODP today. > It's only gpus (I think) which are in this awkward in-between spot > where dynamic memory management really is much wanted, but the hw > kinda sucks. Aside, about 10+ years ago we had a similar problem with > gpu hw, but for security: Many gpu didn't have any kinds of page > tables to isolate different clients from each another. drivers/gpu > fixed this by parsing&validating what userspace submitted to make sure > it's only every accessing its own buffers. Most gpus have become > reasonable nowadays and do have proper per-process pagetables (gpu > process, not the pasid stuff), but even today there's still some of > the old model left in some of the smallest SoC. But I still don't understand why a dma fence is needed inside the GPU driver itself in the notifier. Surely the GPU driver can block and release the notifier directly from its own command processing channel? Why does this fence and all it entails need to leak out across drivers? Jason