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[2003:f1:371d:f700:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id a62sm8033207edf.38.2020.06.20.09.10.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Jun 2020 09:10:20 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, khilman@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 2/3] ARM: dts: meson8m2: add resets for the power domain controller Date: Sat, 20 Jun 2020 18:10:09 +0200 Message-Id: <20200620161010.23171-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200620161010.23171-1-martin.blumenstingl@googlemail.com> References: <20200620161010.23171-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Meson8m2 SoCs has introduced additional reset lines for the VPU compared to Meson8. Also it uses a slightly different VPU clock frequency compared to Meson8 since it can now achieve 364MHz thanks to the addition of the GP_PLL. Add the reset lines, VPU clock configuration and update the compatible string so the implementation differences can be managed. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8m2.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index 2397ba06d608..c7ddbb210366 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -61,6 +61,25 @@ mux { }; }; +&pwrc { + compatible = "amlogic,meson8m2-pwrc"; + resets = <&reset RESET_DBLK>, + <&reset RESET_PIC_DC>, + <&reset RESET_HDMI_APB>, + <&reset RESET_HDMI_SYSTEM_RESET>, + <&reset RESET_VENCI>, + <&reset RESET_VENCP>, + <&reset RESET_VDAC_4>, + <&reset RESET_VENCL>, + <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_RDMA>; + reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", "venci", + "vencp", "vdac", "vencl", "viu", "venc", "rdma"; + assigned-clocks = <&clkc CLKID_VPU>; + assigned-clock-rates = <364000000>; +}; + &saradc { compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; }; -- 2.27.0