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[2003:f1:371d:f700:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id a62sm8033207edf.38.2020.06.20.09.10.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Jun 2020 09:10:21 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, khilman@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 3/3] ARM: dts: meson8b: add power domain controller Date: Sat, 20 Jun 2020 18:10:10 +0200 Message-Id: <20200620161010.23171-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200620161010.23171-1-martin.blumenstingl@googlemail.com> References: <20200620161010.23171-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Meson8b SoCs have a power domain controller which can turn on/off various register areas (such as: Ethernet, VPU, etc.). Add the main "pwrc" controller and configure the Ethernet power domain. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8b.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index ba36168b9c1b..2069c57343e5 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include "meson.dtsi" @@ -433,6 +434,8 @@ ðmac { resets = <&reset RESET_ETHERNET>; reset-names = "stmmaceth"; + + power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; }; &gpio_intc { @@ -449,6 +452,30 @@ clkc: clock-controller { #clock-cells = <1>; #reset-cells = <1>; }; + + pwrc: power-controller { + compatible = "amlogic,meson8b-pwrc"; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&pmu>; + resets = <&reset RESET_DBLK>, + <&reset RESET_PIC_DC>, + <&reset RESET_HDMI_APB>, + <&reset RESET_HDMI_SYSTEM_RESET>, + <&reset RESET_VENCI>, + <&reset RESET_VENCP>, + <&reset RESET_VDAC_4>, + <&reset RESET_VENCL>, + <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_RDMA>; + reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", + "venci", "vencp", "vdac", "vencl", "viu", + "venc", "rdma"; + clocks = <&clkc CLKID_VPU>; + clock-names = "vpu"; + assigned-clocks = <&clkc CLKID_VPU>; + assigned-clock-rates = <182142857>; + }; }; &hwrng { -- 2.27.0