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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id ng12sm3193013pjb.15.2020.06.23.10.33.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jun 2020 10:33:42 -0700 (PDT) Date: Tue, 23 Jun 2020 11:33:40 -0600 From: Mathieu Poirier To: Sai Prakash Ranjan Cc: Suzuki K Poulose , Mike Leach , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephen Boyd Subject: Re: [PATCH] coresight: tmc: Fix TMC mode read in tmc_read_unprepare_etb() Message-ID: <20200623173340.GB1843779@xps15> References: <20200616045441.27483-1-saiprakash.ranjan@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200616045441.27483-1-saiprakash.ranjan@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jun 16, 2020 at 10:24:41AM +0530, Sai Prakash Ranjan wrote: > Reading TMC mode register without proper coresight power > management can lead to exceptions like the one in the call > trace below in tmc_read_unprepare_etb() when the trace data > is read after the sink is disabled. So fix this by having > a check for coresight sysfs mode before reading TMC mode > management register in tmc_read_unprepare_etb() similar to > tmc_read_prepare_etb(). > > SError Interrupt on CPU6, code 0xbe000411 -- SError > pstate: 80400089 (Nzcv daIf +PAN -UAO) > pc : tmc_read_unprepare_etb+0x74/0x108 > lr : tmc_read_unprepare_etb+0x54/0x108 > sp : ffffff80d9507c30 > x29: ffffff80d9507c30 x28: ffffff80b3569a0c > x27: 0000000000000000 x26: 00000000000a0001 > x25: ffffff80cbae9550 x24: 0000000000000010 > x23: ffffffd07296b0f0 x22: ffffffd0109ee028 > x21: 0000000000000000 x20: ffffff80d19e70e0 > x19: ffffff80d19e7080 x18: 0000000000000000 > x17: 0000000000000000 x16: 0000000000000000 > x15: 0000000000000000 x14: 0000000000000000 > x13: 0000000000000000 x12: 0000000000000000 > x11: 0000000000000000 x10: dfffffd000000001 > x9 : 0000000000000000 x8 : 0000000000000002 > x7 : ffffffd071d0fe78 x6 : 0000000000000000 > x5 : 0000000000000080 x4 : 0000000000000001 > x3 : ffffffd071d0fe98 x2 : 0000000000000000 > x1 : 0000000000000004 x0 : 0000000000000001 > Kernel panic - not syncing: Asynchronous SError Interrupt > > Fixes: 4525412a5046 ("coresight: tmc: making prepare/unprepare functions generic") > Reported-by: Mike Leach > Signed-off-by: Sai Prakash Ranjan > --- > drivers/hwtracing/coresight/coresight-tmc-etf.c | 13 ++++++------- > 1 file changed, 6 insertions(+), 7 deletions(-) > And this one too. > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c > index 36cce2bfb744..6375504ba8b0 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c > @@ -639,15 +639,14 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata) > > spin_lock_irqsave(&drvdata->spinlock, flags); > > - /* There is no point in reading a TMC in HW FIFO mode */ > - mode = readl_relaxed(drvdata->base + TMC_MODE); > - if (mode != TMC_MODE_CIRCULAR_BUFFER) { > - spin_unlock_irqrestore(&drvdata->spinlock, flags); > - return -EINVAL; > - } > - > /* Re-enable the TMC if need be */ > if (drvdata->mode == CS_MODE_SYSFS) { > + /* There is no point in reading a TMC in HW FIFO mode */ > + mode = readl_relaxed(drvdata->base + TMC_MODE); > + if (mode != TMC_MODE_CIRCULAR_BUFFER) { > + spin_unlock_irqrestore(&drvdata->spinlock, flags); > + return -EINVAL; > + } > /* > * The trace run will continue with the same allocated trace > * buffer. As such zero-out the buffer so that we don't end > > base-commit: 3d439a6c349778f129de19595db564a8366c3634 > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >