From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5166EC433E0 for ; Wed, 24 Jun 2020 15:05:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2806E2076E for ; Wed, 24 Jun 2020 15:05:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rUWJCnEU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404407AbgFXPF2 (ORCPT ); Wed, 24 Jun 2020 11:05:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404251AbgFXPF0 (ORCPT ); Wed, 24 Jun 2020 11:05:26 -0400 Received: from mail-qt1-x842.google.com (mail-qt1-x842.google.com [IPv6:2607:f8b0:4864:20::842]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3452C061573 for ; Wed, 24 Jun 2020 08:05:26 -0700 (PDT) Received: by mail-qt1-x842.google.com with SMTP id e12so1905452qtr.9 for ; Wed, 24 Jun 2020 08:05:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=E2QT93q4mAHQ58Ta5MG1RGkPeXgSEsXRWz8vivK18vY=; b=rUWJCnEUxL1RvWBYcZKsFagVzZ6RLMKVyhk5QTpU9kLslfZjSvrNUZE7PdQ5RxDD0P YgOA8IDgoRJYQ6doK+Kmn4wJp1BUCsL2EvsAClcifu7NGqOxL4Wna4A65LbMbA/zXSAo YJLyTiyHw84/1y/mS7tD0H5gncGOuqiBBsXp8Ct5eSWGJHG5bzSXFOjSCFwL0oTKYJ1I 9/25K65Q8GS3GQ3p6O9TuDf7hVhGfAxNsgt2gchdNg/3g9rn5kUSP7uLZhi0pqgz+Peh poW+m/N88G7lC+jUnELmccQkQ3SkgUV8Kl9SA9BGzDH5TFV1Q5dbR+qdk+oW/j4sR4hB 1i8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=E2QT93q4mAHQ58Ta5MG1RGkPeXgSEsXRWz8vivK18vY=; b=RvVDQ6RF5G+IXhiunKLLo/gCTrsCc8iZoVAyUCdz/mss70TH8Oo0kPJRAgsfAxXRTV /r4hN1NMLsgpY3iP8XZ0YWZg4m1HgqyxRorkR95zodu47HmNCIZwkNf6aobanu1M1IqS m6787FSCDQoC4crJd05z0MnhG9I42YqunrnDVzQNUmxk2eueDiXfYvMpvu8ildP1vJL1 /M9fpaS4QNbhgsDEb9UunNGtRQAYId4l5GZCXVT3CUJM54LzWkSuqcbyf1zmykXUQ/Tb 3ylXDPNYogWpODDN+EJW8ptbEF3RSGeviAlMB72EuBCAVZvzW/UO4djZ0CPW/jIjyCsR w6Wg== X-Gm-Message-State: AOAM530bjSgSOL8mFpoK+GwBOFHKTHfSZgfgTOyQNcGePBTfIQk/1x6q oGGL88DBwvDIs2gsMdcewDILYtbb X-Google-Smtp-Source: ABdhPJw5x001LVdx99+WaRNGHXQcZtR3Mby0dQmiZDxwN8hW4lPaEGLzCbnZ64vJmPdEZnBwKRDplw== X-Received: by 2002:aed:25fd:: with SMTP id y58mr21018796qtc.310.1593011125659; Wed, 24 Jun 2020 08:05:25 -0700 (PDT) Received: from localhost.localdomain ([72.53.229.195]) by smtp.gmail.com with ESMTPSA id x26sm3434088qtp.54.2020.06.24.08.05.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jun 2020 08:05:25 -0700 (PDT) From: Sven Van Asbroeck X-Google-Original-From: Sven Van Asbroeck To: shawnguo@kernel.org, fugang.duan@nxp.com Cc: Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] ARM: imx6plus: enable internal routing of clk_enet_ref where possible Date: Wed, 24 Jun 2020 11:05:21 -0400 Message-Id: <20200624150521.12196-1-TheSven73@gmail.com> X-Mailer: git-send-email 2.17.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On imx6, the ethernet reference clock (clk_enet_ref) can be generated by either the imx6, or an external source (e.g. an oscillator or the PHY). When generated by the imx6, the clock source (from ANATOP) must be routed to the input of clk_enet_ref via two pads on the SoC, typically via a dedicated track on the PCB. On an imx6 plus however, there is a new setting which enables this clock to be routed internally on the SoC, from its ANATOP clock source, straight to clk_enet_ref, without having to go through the SoC pads. Board designs where the clock is generated by the imx6 should not be affected by routing the clock internally. Therefore on a plus, we can enable internal routing by default. Signed-off-by: Sven Van Asbroeck --- v1 -> v2: - Fabio Estevam: use of_machine_is_compatible() to determine if we are running on an imx6 plus. To: Shawn Guo To: Andy Duan Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org arch/arm/mach-imx/mach-imx6q.c | 18 ++++++++++++++++++ include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + 2 files changed, 19 insertions(+) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 85c084a716ab..2380329ed0b2 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -203,6 +203,24 @@ static void __init imx6q_1588_init(void) else pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); + /* + * On imx6 plus, enet_ref from ANATOP/CCM can be internally routed to + * be the PTP clock source, instead of having to be routed through + * pads. + * Board designs which route the ANATOP/CCM clock through pads are + * unaffected when routing happens internally. So on these designs, + * route internally by default. + */ + if (clksel == IMX6Q_GPR1_ENET_CLK_SEL_ANATOP && cpu_is_imx6q() && + of_machine_is_compatible("fsl,imx6qp")) { + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR5, + IMX6Q_GPR5_ENET_TXCLK_SEL, + IMX6Q_GPR5_ENET_TXCLK_SEL); + else + pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); + } + clk_put(enet_ref); put_ptp_clk: clk_put(ptp_clk); diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index d4b5e527a7a3..eb65d48da0df 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -240,6 +240,7 @@ #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR5_ENET_TXCLK_SEL BIT(9) #define IMX6Q_GPR5_SATA_SW_PD BIT(10) #define IMX6Q_GPR5_SATA_SW_RST BIT(11) -- 2.17.1