From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E43C9C433DF for ; Thu, 25 Jun 2020 14:01:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C3984206B7 for ; Thu, 25 Jun 2020 14:01:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hmNv5x9s" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405278AbgFYOBQ (ORCPT ); Thu, 25 Jun 2020 10:01:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405244AbgFYOBN (ORCPT ); Thu, 25 Jun 2020 10:01:13 -0400 Received: from mail-qt1-x844.google.com (mail-qt1-x844.google.com [IPv6:2607:f8b0:4864:20::844]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5111FC08C5C1 for ; Thu, 25 Jun 2020 07:01:13 -0700 (PDT) Received: by mail-qt1-x844.google.com with SMTP id u12so4620127qth.12 for ; Thu, 25 Jun 2020 07:01:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PkUOCHj9LFPphlCPOdfGOi9fMJfRayuqn+rFrknXVfo=; b=hmNv5x9szlld8JEWZ03cdBMaku4rI3pLsqaeB8MNK/OlxUZA8CPqCjcPHY7kA/hAAG 0vPkM+TjO/RkE+9JWh8ZIuGRKPxqRA0dbRdc7gZLZLqdJfbS4EpbSmSCahWYsJJaA/cy 0TnJdn2mGusb3TWccflxCvSq5M7nPVgRzQ3c3Z3ci6fMPxXA091+LAxT7M+gMvwXuUx6 H0RAzgEL2f6cJcLflRTupK2HR/H3+ugUMctTff20lwkcLoJRxnLoHL5bEVAKxEQB49/0 JNe7b3zXfhrxlExK4wv99znqCJzo14Z35Dxth6ylMlUF0VfVn2qbvotdOW+p7DZFkH/U sX5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PkUOCHj9LFPphlCPOdfGOi9fMJfRayuqn+rFrknXVfo=; b=RZty1SR8UgcDwnJfphKv3+lydlQ7Wnbv2RwClRN8IutbAklqjqO+D11JLtmElGnoko L6ytWKZZE60ueFWB6zboK59uk0b9XZlBptAuJSwVsBbXUgalXQIveZNeF+FlHc+MlYzj 0K+3PNavgJVpCVUloQYaKK7RIySkUifVjRZJvlIF33dpUStwB+e85TFXCZfXUtn6/aU5 1h/JocteucUZrNytu6YMa0yn5CcyLJvk1y0ZBfMQjIaPJ24wO5tuQladduGzFAdTcl7t DLDSAtIISBg9lNy34GPsA2Vmgn7jomLEUOG+WADxCBmA7DgYm2Sh0G3cQn3RmM46nT9j McWQ== X-Gm-Message-State: AOAM530t+uu5uTrqX3I6zQzBOjl/P6mHw6SiW8ydBK3qfuK2R5/6ng07 2H2xDD4GnQIZDpj19S8go3g= X-Google-Smtp-Source: ABdhPJz0TnsQuAj2jQwYLjbicbfNVB1Hjk7FRyAAAWCBwd9Iio2s6flRsVSg3FsUXtCMMDxVSM+P5A== X-Received: by 2002:ac8:6d17:: with SMTP id o23mr17470321qtt.127.1593093672273; Thu, 25 Jun 2020 07:01:12 -0700 (PDT) Received: from localhost.localdomain ([72.53.229.195]) by smtp.gmail.com with ESMTPSA id f4sm5337691qtv.59.2020.06.25.07.01.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2020 07:01:11 -0700 (PDT) From: Sven Van Asbroeck X-Google-Original-From: Sven Van Asbroeck To: shawnguo@kernel.org, fugang.duan@nxp.com Cc: Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/2] ARM: imx6plus: enable internal routing of clk_enet_ref where possible Date: Thu, 25 Jun 2020 10:01:05 -0400 Message-Id: <20200625140105.14999-2-TheSven73@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200625140105.14999-1-TheSven73@gmail.com> References: <20200625140105.14999-1-TheSven73@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On imx6, the ethernet reference clock (clk_enet_ref) can be generated by either the imx6, or an external source (e.g. an oscillator or the PHY). When generated by the imx6, the clock source (from ANATOP) must be routed to the input of clk_enet_ref via two pads on the SoC, typically via a dedicated track on the PCB. On an imx6 plus however, there is a new setting which enables this clock to be routed internally on the SoC, from its ANATOP clock source, straight to clk_enet_ref, without having to go through the SoC pads. Board designs where the clock is generated by the imx6 should not be affected by routing the clock internally. Therefore on a plus, we can enable internal routing by default. Signed-off-by: Sven Van Asbroeck --- v3 -> v4: - avoid double-check for IS_ERR(gpr) by including Fabio Estevam's patch. v2 -> v3: - remove check for imx6q, which is already implied when of_machine_is_compatible("fsl,imx6qp") v1 -> v2: - Fabio Estevam: use of_machine_is_compatible() to determine if we are running on an imx6 plus. To: Shawn Guo To: Andy Duan Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org arch/arm/mach-imx/mach-imx6q.c | 14 ++++++++++++++ include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + 2 files changed, 15 insertions(+) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index ae89ad93ca83..07cfe0d349c3 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -204,6 +204,20 @@ static void __init imx6q_1588_init(void) regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_ENET_CLK_SEL_MASK, clksel); + /* + * On imx6 plus, enet_ref from ANATOP/CCM can be internally routed to + * be the PTP clock source, instead of having to be routed through + * pads. + * Board designs which route the ANATOP/CCM clock through pads are + * unaffected when routing happens internally. So on these designs, + * route internally by default. + */ + if (clksel == IMX6Q_GPR1_ENET_CLK_SEL_ANATOP && + of_machine_is_compatible("fsl,imx6qp")) + regmap_update_bits(gpr, IOMUXC_GPR5, + IMX6Q_GPR5_ENET_TXCLK_SEL, + IMX6Q_GPR5_ENET_TXCLK_SEL); + clk_put(enet_ref); put_ptp_clk: clk_put(ptp_clk); diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index d4b5e527a7a3..eb65d48da0df 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -240,6 +240,7 @@ #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR5_ENET_TXCLK_SEL BIT(9) #define IMX6Q_GPR5_SATA_SW_PD BIT(10) #define IMX6Q_GPR5_SATA_SW_RST BIT(11) -- 2.17.1