From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7A34C433E0 for ; Fri, 26 Jun 2020 13:23:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A01542078D for ; Fri, 26 Jun 2020 13:23:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1593177808; bh=eLUtMNXs0fYMI6cz6qlvIpFMySMSeTOQYK+CTrq5IHc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=bHZr1IuRcbVJ0baXVB1v7HiKTh/xkmp3o/zNc/IcZvvi1i8RVz3Gx6k0xJTKFT4HF Ugu9nDxfZHCmmS4rsm2syUJYALhVvLVy0csDASyWacTLwP+NWAMXelwOt0cciSiTzQ 1PVLS4wLP5P0eEzrhcU7ioxlNodzH4d9Vf2/cfhA= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728277AbgFZNX1 (ORCPT ); Fri, 26 Jun 2020 09:23:27 -0400 Received: from mail.kernel.org ([198.145.29.99]:34978 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725864AbgFZNXZ (ORCPT ); Fri, 26 Jun 2020 09:23:25 -0400 Received: from pali.im (pali.im [31.31.79.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E68BC2078D; Fri, 26 Jun 2020 13:23:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1593177805; bh=eLUtMNXs0fYMI6cz6qlvIpFMySMSeTOQYK+CTrq5IHc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ViFJdl33+SQO0HSremYUDH6RB/AlDLXkbLcptQ6dttFIB0MRREVlGkxng12H89P3h Ykk/jY4yd2dA1NXQsM/YnKERkJsvCcxWtK2/4YEjYSs+quabNSiSvWRubAJqBsKbfF LRb+KiIF8A/Fuqx2vr9LCDRaoIXX/T25PwGM/4kA= Received: by pali.im (Postfix) id 065AD890; Fri, 26 Jun 2020 15:23:22 +0200 (CEST) Date: Fri, 26 Jun 2020 15:23:22 +0200 From: Pali =?utf-8?B?Um9ow6Fy?= To: Pavel Machek Cc: Greg Kroah-Hartman , linux-kernel@vger.kernel.org, stable@vger.kernel.org, Tomasz Maciej Nowak , Lorenzo Pieralisi , Rob Herring , Thomas Petazzoni , Sasha Levin Subject: Re: [PATCH 4.19 023/206] PCI: aardvark: Dont blindly enable ASPM L0s and dont write to read-only register Message-ID: <20200626132322.j5wwyps7rj3c3eeg@pali> References: <20200623195316.864547658@linuxfoundation.org> <20200623195318.115434987@linuxfoundation.org> <20200626125350.GA29985@duo.ucw.cz> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200626125350.GA29985@duo.ucw.cz> User-Agent: NeoMutt/20180716 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello! On Friday 26 June 2020 14:53:50 Pavel Machek wrote: > Hi! > > > [ Upstream commit 90c6cb4a355e7befcb557d217d1d8b8bd5875a05 ] > > > > Trying to change Link Status register does not have any effect as this > > is a read-only register. Trying to overwrite bits for Negotiated Link > > Width does not make sense. > > I don't quite get it. This says register is read only... > > > In future proper change of link width can be done via Lane Count Select > > bits in PCIe Control 0 register. > > > > Trying to unconditionally enable ASPM L0s via ASPM Control bits in Link > > Control register is wrong. There should be at least some detection if > > endpoint supports L0s as isn't mandatory. > > ....and this says it is wrong to set the bits as ASPM L0 is not > mandatory. Negotiated Link Width is in read-only 16bit Link Status register. ASPM Control bits are in read-write 16bit Link Control register. > > +++ b/drivers/pci/controller/pci-aardvark.c > > @@ -321,10 +321,6 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) > > > > advk_pcie_wait_for_link(pcie); > > > > - reg = PCIE_CORE_LINK_L0S_ENTRY | > > - (1 << PCIE_CORE_LINK_WIDTH_SHIFT); > > - advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); > > - > > reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); > > reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | > > PCIE_CORE_CMD_IO_ACCESS_EN | > > ...but we only do single write. > > So which is it? That single write was via 32bit memory access which tried to overwrite both registers (Link Status and Link Control) at the same time. > Best regards, > Pavel > -- > (english) http://www.livejournal.com/~pavelmachek > (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html