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Tue, 30 Jun 2020 15:49:56 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 48C92302753; Tue, 30 Jun 2020 17:49:54 +0200 (CEST) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 3570D20CF3979; Tue, 30 Jun 2020 17:49:54 +0200 (CEST) Date: Tue, 30 Jun 2020 17:49:54 +0200 From: Peter Zijlstra To: kan.liang@linux.intel.com Cc: mingo@redhat.com, acme@kernel.org, tglx@linutronix.de, bp@alien8.de, x86@kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@redhat.com, namhyung@kernel.org, dave.hansen@intel.com, yu-cheng.yu@intel.com, bigeasy@linutronix.de, gorcunov@gmail.com, hpa@zytor.com, alexey.budankov@linux.intel.com, eranian@google.com, ak@linux.intel.com, like.xu@linux.intel.com, yao.jin@linux.intel.com, wei.w.wang@intel.com Subject: Re: [PATCH V2 14/23] perf/x86/intel/lbr: Support Architectural LBR Message-ID: <20200630154954.GU4781@hirez.programming.kicks-ass.net> References: <1593195620-116988-1-git-send-email-kan.liang@linux.intel.com> <1593195620-116988-15-git-send-email-kan.liang@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1593195620-116988-15-git-send-email-kan.liang@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jun 26, 2020 at 11:20:11AM -0700, kan.liang@linux.intel.com wrote: > + if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) > + intel_pmu_arch_lbr_init(); > +static inline bool is_lbr_call_stack_bit_set(u64 config) > +{ > + if (x86_pmu.arch_lbr) > + return !!(config & ARCH_LBR_CALL_STACK); > + > + return !!(config & LBR_CALL_STACK); > +} > + if (!x86_pmu.arch_lbr && !pmi && cpuc->lbr_sel) > wrmsrl(MSR_LBR_SELECT, lbr_select); > + if (!x86_pmu.arch_lbr) > + debugctl |= DEBUGCTLMSR_LBR; > + if (x86_pmu.arch_lbr) > + wrmsrl(MSR_ARCH_LBR_CTL, lbr_select | ARCH_LBR_CTL_LBREN); > } etc... > +void __init intel_pmu_arch_lbr_init(void) > +{ > + unsigned int unused_edx; > + u64 lbr_nr; > + > + /* Arch LBR Capabilities */ > + cpuid(28, &x86_pmu.lbr_eax.full, &x86_pmu.lbr_ebx.full, > + &x86_pmu.lbr_ecx.full, &unused_edx); > + > + lbr_nr = x86_pmu_get_max_arch_lbr_nr(); > + if (!lbr_nr) > + return; > + > + /* Apply the max depth of Arch LBR */ > + if (wrmsrl_safe(MSR_ARCH_LBR_DEPTH, lbr_nr)) > + return; > + > + x86_pmu.lbr_nr = lbr_nr; > + x86_get_pmu()->task_ctx_size = sizeof(struct x86_perf_task_context_arch_lbr) + > + lbr_nr * sizeof(struct lbr_entry); > + > + x86_pmu.lbr_from = MSR_ARCH_LBR_FROM_0; > + x86_pmu.lbr_to = MSR_ARCH_LBR_TO_0; > + x86_pmu.lbr_info = MSR_ARCH_LBR_INFO_0; > + > + /* LBR callstack requires both CPL and Branch Filtering support */ > + if (!x86_pmu.lbr_ebx.split.lbr_cpl || > + !x86_pmu.lbr_ebx.split.lbr_filter || > + !x86_pmu.lbr_ebx.split.lbr_call_stack) > + arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] = LBR_NOT_SUPP; > + > + if (!x86_pmu.lbr_ebx.split.lbr_cpl) { > + arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_NOT_SUPP; > + arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_NOT_SUPP; > + } else if (!x86_pmu.lbr_ebx.split.lbr_filter) { > + arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_NOT_SUPP; > + arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_NOT_SUPP; > + arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_NOT_SUPP; > + arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_NOT_SUPP; > + arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_NOT_SUPP; > + arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_NOT_SUPP; > + arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_NOT_SUPP; > + } > + > + x86_pmu.lbr_ctl_mask = ARCH_LBR_CTL_MASK; > + x86_pmu.lbr_ctl_map = arch_lbr_ctl_map; > + > + if (!x86_pmu.lbr_ebx.split.lbr_cpl && !x86_pmu.lbr_ebx.split.lbr_filter) > + x86_pmu.lbr_ctl_map = NULL; > + > + x86_pmu.lbr_reset = intel_pmu_arch_lbr_reset; > + x86_pmu.lbr_read = intel_pmu_arch_lbr_read; > + x86_pmu.lbr_save = intel_pmu_arch_lbr_save; > + x86_pmu.lbr_restore = intel_pmu_arch_lbr_restore; > + > + x86_pmu.arch_lbr = true; > + pr_cont("Architectural LBR, "); > +} How about we make this here clear FEATURE_ARCH_LBR if it fails and then do away with x86_pmu.arch_lbr and use static_cpu_has(X86_FEATURE_ARCH_LBR) a lot more?