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Wed, 15 Jul 2020 07:15:56 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Rob Herring , Daniel Lezcano , Thomas Gleixner Cc: Damien Le Moal , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel , Palmer Dabbelt Subject: [PATCH v3 4/4] dt-bindings: timer: Add CLINT bindings Date: Wed, 15 Jul 2020 12:45:05 +0530 Message-Id: <20200715071506.10994-5-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200715071506.10994-1-anup.patel@wdc.com> References: <20200715071506.10994-1-anup.patel@wdc.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: PN1PR0101CA0047.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:c::33) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (103.15.57.135) by PN1PR0101CA0047.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:c::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3195.18 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: bjmXX+mT0UdynPpPXP+2O4kocSeYkelM1klNDTjTAPutqgDNeLUHCHcuhU4VCoil7CUlFccxhItVVU0ewvo6QDrrUGiQohEpZjrAjPANSfyPx8Z8W/Wra3rkG6xNqRpGFBDzdCmHGbTxpKVKN4nIkhVU9eIdd/FKfxEQl5PQ6lDr7eQiO3LPg95/+/qm7Q+9PYRnbqD4u4AiDskrw6EVRoU4BBPR0FQfVLupyGS+tb2rm6FOzIVrV7jWAK2R7P9IonXyjEGDcZpVGSfVgZg8Q5ZfqYJiLLnJK9b44/ptMUnYuRBlW+BOQoTADwf9qNzpSkcT9axRulp+zClygahE4yvSFwUm6anYaK8X5K/3Uk297G0wodCfdw5bRSQj0Gm1j3Cmbt71xZEN3kr6hop2qkM0ukmYzJZZnMDFZ7W7m55eeZgcy+WrXPXuNLPXR9uUDwWeIp9Q5btVz9vY5DZnHIgIbrs7Ntnx4jqQW3YgYlM= X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 28026172-b822-4b50-19bb-08d8288eeaf2 X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2020 07:15:56.7755 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: g7zY8gNgB5dwCKhjpIW9g8jHlEk/sm3jB4WtuvusxBKPHhxP7+lJelsweZksuZgPpwCF45ijJHkdYZpdjGMVUw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR04MB4329 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We add DT bindings documentation for CLINT device. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt --- .../bindings/timer/sifive,clint.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.yaml diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml new file mode 100644 index 000000000000..f5579a759ef5 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/sifive,clint.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Core Local Interruptor + +maintainers: + - Palmer Dabbelt + - Anup Patel + +description: + SiFive (and other RISC-V) SOCs include an implementation of the SiFive + Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor + interrupts. It directly connects to the timer and inter-processor interrupt + lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local + interrupt controller is the parent interrupt controller for CLINT device. + The clock frequency of CLINT is specified via "timebase-frequency" DT + property of "/cpus" DT node. The "timebase-frequency" DT property is + described in Documentation/devicetree/bindings/riscv/cpus.yaml + +properties: + compatible: + items: + - const: sifive,fu540-c000-clint + - const: sifive,clint0 + + description: + Should be "sifive,-clint" and "sifive,clint". + Supported compatible strings are - + "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated + onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive + CLINT v0 IP block with no chip integration tweaks. + Please refer to sifive-blocks-ip-versioning.txt for details + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + clint@2000000 { + compatible = "sifive,clint0", "sifive,fu540-c000-clint"; + interrupts-extended = <&cpu1-intc 3 &cpu1-intc 7 + &cpu2-intc 3 &cpu2-intc 7 + &cpu3-intc 3 &cpu3-intc 7 + &cpu4-intc 3 &cpu4-intc 7>; + reg = <0x2000000 0x4000000>; + }; +... -- 2.25.1