From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF488C433E1 for ; Fri, 17 Jul 2020 10:40:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9137720734 for ; Fri, 17 Jul 2020 10:40:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726210AbgGQKkV (ORCPT ); Fri, 17 Jul 2020 06:40:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725864AbgGQKkU (ORCPT ); Fri, 17 Jul 2020 06:40:20 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B857FC061755 for ; Fri, 17 Jul 2020 03:40:20 -0700 (PDT) Received: from xps.home (unknown [IPv6:2a01:e35:2fb5:1510:c567:382e:1974:9868]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: aferraris) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id CDB8B2A5C77; Fri, 17 Jul 2020 11:40:18 +0100 (BST) From: Arnaud Ferraris To: alsa-devel@alsa-project.org Cc: Timur Tabi , Nicolin Chen , Xiubo Li , Fabio Estevam , Shengjiu Wang , Liam Girdwood , Mark Brown , linux-kernel@vger.kernel.org, kernel@collabora.com, Arnaud Ferraris Subject: [PATCH v3 1/1] ASoC: fsl_asrc: make sure the input and output clocks are different Date: Fri, 17 Jul 2020 12:38:58 +0200 Message-Id: <20200717103857.31877-2-arnaud.ferraris@collabora.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200717103857.31877-1-arnaud.ferraris@collabora.com> References: <20200716232000.GA27246@Asurada-Nvidia> <20200717103857.31877-1-arnaud.ferraris@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current clock selection algorithm might select the same clock for both input and output when, for instance, the output sample rate is a multiple of the input rate. In that case, both selectable clocks will be multiples of both the input and output sample rates, and therefore the first of these clocks will be selected for both input and output, leading to miscalculation of the dividers for either the input or output side. Example: Input uses clock A (512kHz) and has a sample rate of 8kHz Output uses clock B (1024kHz) and has a sample rate of 16kHz In this case, the algorithm will select clock A for both input and output: the input divider will therefore be calculated properly (512 / 8 => 64), but the output divider's value will be only half the expected value (512 / 16 => 32 instead of 1024 / 16 => 64). This patch makes sure it always selects distinct input and output clocks. Signed-off-by: Arnaud Ferraris --- sound/soc/fsl/fsl_asrc.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c index 02c81d2e34ad..de10c208d3c8 100644 --- a/sound/soc/fsl/fsl_asrc.c +++ b/sound/soc/fsl/fsl_asrc.c @@ -608,8 +608,8 @@ static void fsl_asrc_select_clk(struct fsl_asrc_priv *asrc_priv, { struct fsl_asrc_pair_priv *pair_priv = pair->private; struct asrc_config *config = pair_priv->config; - int rate[2], select_clk[2]; /* Array size 2 means IN and OUT */ - int clk_rate, clk_index; + int rate[2], select_clk[2], clk_index[2]; /* Array size 2 means IN and OUT */ + int clk_rate; int i = 0, j = 0; rate[IN] = in_rate; @@ -618,11 +618,15 @@ static void fsl_asrc_select_clk(struct fsl_asrc_priv *asrc_priv, /* Select proper clock source for internal ratio mode */ for (j = 0; j < 2; j++) { for (i = 0; i < ASRC_CLK_MAP_LEN; i++) { - clk_index = asrc_priv->clk_map[j][i]; - clk_rate = clk_get_rate(asrc_priv->asrck_clk[clk_index]); - /* Only match a perfect clock source with no remainder */ + clk_index[j] = asrc_priv->clk_map[j][i]; + clk_rate = clk_get_rate(asrc_priv->asrck_clk[clk_index[j]]); + /* + * Only match a perfect clock source with no remainder + * and make sure the input & output clocks are different + */ if (clk_rate != 0 && (clk_rate / rate[j]) <= 1024 && - (clk_rate % rate[j]) == 0) + (clk_rate % rate[j]) == 0 && + (j == 0 || clk_index[j] != clk_index[j - 1])) break; } -- 2.27.0