From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7D62C433F2 for ; Sat, 18 Jul 2020 19:35:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C608420702 for ; Sat, 18 Jul 2020 19:35:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="JzUqKQqN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728239AbgGRTfW (ORCPT ); Sat, 18 Jul 2020 15:35:22 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:14280 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728127AbgGRTfP (ORCPT ); Sat, 18 Jul 2020 15:35:15 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sat, 18 Jul 2020 12:34:15 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sat, 18 Jul 2020 12:35:15 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sat, 18 Jul 2020 12:35:15 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 18 Jul 2020 19:35:11 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 18 Jul 2020 19:35:10 +0000 Received: from vdumpa-ubuntu.nvidia.com (Not Verified[172.17.173.140]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sat, 18 Jul 2020 12:35:10 -0700 From: Krishna Reddy To: , , , , , CC: , , , , , , , , , , , , , , Krishna Reddy , Rob Herring Subject: [PATCH v11 4/5] dt-bindings: arm-smmu: add binding for Tegra194 SMMU Date: Sat, 18 Jul 2020 12:34:56 -0700 Message-ID: <20200718193457.30046-5-vdumpa@nvidia.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200718193457.30046-1-vdumpa@nvidia.com> References: <20200718193457.30046-1-vdumpa@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595100855; bh=Y2GkTsQPdZaXJ3/ZSfPDjVUpBzjiUKOjktXU6d24nFk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=JzUqKQqNncVSoo1ttjCQA2/b08DCu9lGElLEyC7u6129abh0YWGJLXNmcf5JCG3Qt YK52ulKn10OO8sT57ZA6a3Ln3/0UR9LwvuGtKU9bgL9VfQEa4DgZNpvVSRwa+tj8tt iHvaYJAMWlvn0p18m0Yysf1H702r0+TH36/jdb9drqvAFl/8rRaNrvkiPhIlI0p20d zIBc7HxKFuR5Qo2dRmcdffP1n15fw9nu/Q0Y5V5d9PqgHrxs0BY+s5I0JrbFCFClun +2hPd4wifnK8zisRUUkauu0SGnGldYq9rMz7nzpo5V1ijCVrEujQ1lDxGgOhHPKTbn WTerEMONdvyWg== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding for NVIDIA's Tegra194 SoC SMMU. Reviewed-by: Jon Hunter Reviewed-by: Rob Herring Reviewed-by: Robin Murphy Signed-off-by: Krishna Reddy --- .../devicetree/bindings/iommu/arm,smmu.yaml | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Docume= ntation/devicetree/bindings/iommu/arm,smmu.yaml index 93fb9fe068b9..503160a7b9a0 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -44,6 +44,11 @@ properties: items: - const: marvell,ap806-smmu-500 - const: arm,mmu-500 + - description: NVIDIA SoCs that program two ARM MMU-500s identically + items: + - enum: + - nvidia,tegra194-smmu + - const: nvidia,smmu-500 - items: - const: arm,mmu-500 - const: arm,smmu-v2 @@ -61,7 +66,8 @@ properties: - cavium,smmu-v2 =20 reg: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 '#global-interrupts': description: The number of global interrupts exposed by the device. @@ -144,6 +150,23 @@ required: =20 additionalProperties: false =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-smmu + then: + properties: + reg: + minItems: 2 + maxItems: 2 + else: + properties: + reg: + maxItems: 1 + examples: - |+ /* SMMU with stream matching or stream indexing */ --=20 2.26.2