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Tue, 28 Jul 2020 08:30:40 +0000 From: Akshu Agrawal To: akshu.agrawal@amd.com Cc: sboyd@kernel.org, rafael@kernel.org, Michael Turquette , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list) Subject: [v3 4/4] clk: x86: Support RV architecture Date: Tue, 28 Jul 2020 13:58:56 +0530 Message-Id: <20200728082857.10829-5-akshu.agrawal@amd.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200728082857.10829-1-akshu.agrawal@amd.com> References: <20200728082857.10829-1-akshu.agrawal@amd.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: MA1PR01CA0160.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::30) To DM5PR1201MB0188.namprd12.prod.outlook.com (2603:10b6:4:56::12) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from local.mshome.net (122.171.179.172) by MA1PR01CA0160.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3216.22 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: SlSXSO/UbQowtsdJcv5NjsMW7DqaZ1snSQAXzPSTNk+3jTqVu4D14RGPBHqwB6MGrp6J2yRev7F96vjt+kVjl3tBmtBtuL0w5s7jakwj32ZRbsU5W/3DsO7W6ilMCERGoTMBi1SmSshsuJhXX01tLQcD2dRLj8ZIP+7ypBm6XgqzIlBp5rXEwK5XrKr7VBlqjrsGpLSLH/zrHRtYjVLY99JeVuy+Dx7tzTv3deyQc3gKy21cktfert7zubcp4qqbGl+e3u1lnVF/HQkqZJ5FlvBeFdYGHtFAvIfjGLS57coXALEYlORDzHs0Lyq3k4wBr/9ckMuPJwDrdonQiN2OLUtRwLIP3hov0RzFyG3gGrmosZQqbPc7nRs8Q61M0L7ThcKek1zKcIqL6ahN+Dr36fiIJU1CGdCPJOcfcHQOvv0jMfgkt+4OHfDyVRjrCVNJLKya05N7MyKcGyPbztq1zl1aio6qPw1lDc66lFLb5dg= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 92d94503-5747-4c53-0d24-08d832d082c3 X-MS-Exchange-CrossTenant-AuthSource: DM5PR1201MB0188.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jul 2020 08:30:40.5480 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 73KVX+A8h/+XMT7IHBtX/iKMj/cI+2RPaevSQcpQHfkSPHHQfS7wmdndeU4tIt6ysfQouWXlLTBnTuNtgscKfg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1468 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There is minor difference between previous family of SoC and the current one. Which is the there is only 48Mh fixed clk. There is no mux and no option to select another freq as there in previous. Signed-off-by: Akshu Agrawal --- v2: Consolidated the loops in remove. v3: Removed negation in condition to make it simple drivers/clk/x86/clk-fch.c | 53 ++++++++++++++++++++++++++++----------- 1 file changed, 38 insertions(+), 15 deletions(-) diff --git a/drivers/clk/x86/clk-fch.c b/drivers/clk/x86/clk-fch.c index b252f0cf0628..8f7c5142b0f0 100644 --- a/drivers/clk/x86/clk-fch.c +++ b/drivers/clk/x86/clk-fch.c @@ -26,6 +26,10 @@ #define ST_CLK_GATE 3 #define ST_MAX_CLKS 4 +#define RV_CLK_48M 0 +#define RV_CLK_GATE 1 +#define RV_MAX_CLKS 2 + static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" }; static struct clk_hw *hws[ST_MAX_CLKS]; @@ -37,33 +41,52 @@ static int fch_clk_probe(struct platform_device *pdev) if (!fch_data || !fch_data->base) return -EINVAL; - hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", NULL, 0, - 48000000); - hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", NULL, 0, - 25000000); + if (!fch_data->is_rv) { + hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", + NULL, 0, 48000000); + hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", + NULL, 0, 25000000); + + hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux", + clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents), + 0, fch_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, + NULL); - hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux", - clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents), - 0, fch_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL); + clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk); - clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk); + hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", + "oscout1_mux", 0, fch_data->base + MISCCLKCNTL1, + OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL); - hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux", - 0, fch_data->base + MISCCLKCNTL1, OSCCLKENB, - CLK_GATE_SET_TO_DISABLE, NULL); + devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE], + "oscout1", NULL); + } else { + hws[RV_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", + NULL, 0, 48000000); - devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE], "oscout1", - NULL); + hws[RV_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", + "clk48MHz", 0, fch_data->base + MISCCLKCNTL1, + OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL); + + devm_clk_hw_register_clkdev(&pdev->dev, hws[RV_CLK_GATE], + "oscout1", NULL); + } return 0; } static int fch_clk_remove(struct platform_device *pdev) { - int i; + int i, clks; + struct fch_clk_data *fch_data; - for (i = 0; i < ST_MAX_CLKS; i++) + fch_data = dev_get_platdata(&pdev->dev); + + clks = fch_data->is_rv ? RV_MAX_CLKS : ST_MAX_CLKS; + + for (i = 0; i < clks; i++) clk_hw_unregister(hws[i]); + return 0; } -- 2.20.1