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[153.199.2.183]) by smtp.googlemail.com with ESMTPSA id fv21sm2583142pjb.16.2020.08.05.04.01.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2020 04:01:20 -0700 (PDT) From: Daniel Palmer To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, robh+dt@kernel.org, arnd@arndb.de, Daniel Palmer Subject: [PATCH 0/3] irqchip: mstar: msc313 intc driver Date: Wed, 5 Aug 2020 20:00:49 +0900 Message-Id: <20200805110052.2655487-1-daniel@0x0f.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This driver adds support for the interrupt controllers present between the various IP blocks and the ARM GIC in MStar/SigmaStar Armv7 SoCs. All of the chips so far have two instances of this controller. One instance controls what are called "IRQ" interrupts by the vendor code I have seen. The other instance controls what are called "FIQ" interrupts by the vendor code. Presumably because they can be FIQ interrupts. Right now the FIQ bypass is disabled in the GIC so they operate just the same as the IRQ interrupts. The register layouts are the same for both. The FIQ one needs to have the status bit cleared on EOI so that difference is handled by a compatible string difference. I initially made this an RFC because this is my first interrupt controller driver and I expect to have made a bunch of mistakes. I've cleaned this up a bit since then but I still expect it's not 100% correct. Especially the offset to map the INTC interrupt to the GIC interrupt. Daniel Palmer (3): dt: bindings: interrupt-controller: Add binding description for msc313-intc irqchip: mstar: msc313-intc interrupt controller driver ARM: mstar: Add interrupt controller to base dtsi .../mstar,msc313-intc.yaml | 79 +++++++ MAINTAINERS | 2 + arch/arm/boot/dts/mstar-v7.dtsi | 20 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-msc313-intc.c | 210 ++++++++++++++++++ 5 files changed, 312 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.yaml create mode 100644 drivers/irqchip/irq-msc313-intc.c -- 2.27.0