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[153.199.2.183]) by smtp.googlemail.com with ESMTPSA id fv21sm2583142pjb.16.2020.08.05.04.01.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2020 04:01:31 -0700 (PDT) From: Daniel Palmer To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, robh+dt@kernel.org, arnd@arndb.de, Daniel Palmer , Willy Tarreau Subject: [PATCH 3/3] ARM: mstar: Add interrupt controller to base dtsi Date: Wed, 5 Aug 2020 20:00:52 +0900 Message-Id: <20200805110052.2655487-4-daniel@0x0f.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200805110052.2655487-1-daniel@0x0f.com> References: <20200805110052.2655487-1-daniel@0x0f.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the IRQ and FIQ intc instances to the base MStar/SigmaStar v7 dtsi. All of the known SoCs have both and at the same place with their common IPs using the same interrupt lines. Signed-off-by: Daniel Palmer Tested-by: Willy Tarreau --- arch/arm/boot/dts/mstar-v7.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 3b7b9b793736..2b3bb0886d1a 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -85,6 +85,26 @@ reboot { mask = <0x79>; }; + intc_fiq: intc@201310 { + compatible = "mstar,msc313-intc-fiq"; + interrupt-controller; + reg = <0x201310 0x40>; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + mstar,gic-offset = <96>; + mstar,nr-interrupts = <32>; + }; + + intc_irq: intc@201350 { + compatible = "mstar,msc313-intc-irq"; + interrupt-controller; + reg = <0x201350 0x40>; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + mstar,gic-offset = <32>; + mstar,nr-interrupts = <64>; + }; + l3bridge: l3bridge@204400 { compatible = "mstar,l3bridge"; reg = <0x204400 0x200>; -- 2.27.0