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Rao" , Ian Rogers , Kemeng Shi , James Clark , Wei Li , Adrian Hunter , Al Grant , linux-kernel@vger.kernel.org, Mathieu Poirier , Mike Leach Cc: Leo Yan Subject: [PATCH RESEND v1 11/11] perf arm-spe: Set sample's data source field Date: Thu, 6 Aug 2020 11:07:27 +0800 Message-Id: <20200806030727.30267-12-leo.yan@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200806030727.30267-1-leo.yan@linaro.org> References: <20200806030727.30267-1-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The sample structure contains the field 'data_src' which is used to tell the detailed info for data operations, e.g. this field indicates the data operation is loading or storing, on which cache level, it's snooping or remote accessing, etc. At the end, the 'data_src' will be parsed by perf memory tool to display human readable strings. This patch is to fill the 'data_src' field in the synthesized samples base on different types. Now support types for Level 1 dcache miss, Level 1 dcache hit, Last level cache miss, Last level cache access, TLB miss, TLB hit, remote access for other socket. Note, current perf tool can display statistics for L1/L2/L3 caches but it doesn't support the 'last level cache'. To fit into current implementation, 'data_src' field uses L3 cache for last level cache. Signed-off-by: Leo Yan --- tools/perf/util/arm-spe.c | 87 +++++++++++++++++++++++++++++++++++---- 1 file changed, 79 insertions(+), 8 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 74308a72b000..3114f059fc2f 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -259,7 +259,7 @@ arm_spe_deliver_synth_event(struct arm_spe *spe, } static int arm_spe__synth_mem_sample(struct arm_spe_queue *speq, - u64 spe_events_id) + u64 spe_events_id, u64 data_src) { struct arm_spe *spe = speq->spe; struct arm_spe_record *record = &speq->decoder->record; @@ -272,6 +272,7 @@ static int arm_spe__synth_mem_sample(struct arm_spe_queue *speq, sample.stream_id = spe_events_id; sample.addr = record->addr; sample.phys_addr = record->phys_addr; + sample.data_src = data_src; return arm_spe_deliver_synth_event(spe, speq, event, &sample); } @@ -293,21 +294,74 @@ static int arm_spe__synth_branch_sample(struct arm_spe_queue *speq, return arm_spe_deliver_synth_event(spe, speq, event, &sample); } +static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, + int type) +{ + union perf_mem_data_src data_src = { 0 }; + + if (record->op == ARM_SPE_LD) + data_src.mem_op = PERF_MEM_OP_LOAD; + else + data_src.mem_op = PERF_MEM_OP_STORE; + + switch (type) { + case ARM_SPE_L1D_MISS: + data_src.mem_lvl_num = PERF_MEM_LVLNUM_L1; + data_src.mem_lvl = PERF_MEM_LVL_MISS | PERF_MEM_LVL_L1; + break; + case ARM_SPE_L1D_ACCESS: + data_src.mem_lvl_num = PERF_MEM_LVLNUM_L1; + data_src.mem_lvl = PERF_MEM_LVL_HIT | PERF_MEM_LVL_L1; + break; + case ARM_SPE_LLC_MISS: + data_src.mem_lvl_num = PERF_MEM_LVLNUM_L3; + data_src.mem_lvl = PERF_MEM_LVL_MISS | PERF_MEM_LVL_L3; + break; + case ARM_SPE_LLC_ACCESS: + data_src.mem_lvl_num = PERF_MEM_LVLNUM_L3; + data_src.mem_lvl = PERF_MEM_LVL_HIT | PERF_MEM_LVL_L3; + break; + case ARM_SPE_TLB_MISS: + data_src.mem_dtlb = PERF_MEM_TLB_WK | PERF_MEM_TLB_MISS; + break; + case ARM_SPE_TLB_ACCESS: + data_src.mem_dtlb = PERF_MEM_TLB_WK | PERF_MEM_TLB_HIT; + break; + case ARM_SPE_REMOTE_ACCESS: + data_src.mem_lvl_num = PERF_MEM_LVLNUM_ANY_CACHE; + data_src.mem_lvl = PERF_MEM_LVL_HIT | PERF_MEM_LVL_REM_CCE1; + break; + default: + break; + } + + return data_src.val; +} + static int arm_spe_sample(struct arm_spe_queue *speq) { const struct arm_spe_record *record = &speq->decoder->record; struct arm_spe *spe = speq->spe; + u64 data_src; int err; if (spe->sample_flc) { if (record->type & ARM_SPE_L1D_MISS) { - err = arm_spe__synth_mem_sample(speq, spe->l1d_miss_id); + data_src = arm_spe__synth_data_source(record, + ARM_SPE_L1D_MISS); + + err = arm_spe__synth_mem_sample(speq, spe->l1d_miss_id, + data_src); if (err) return err; } if (record->type & ARM_SPE_L1D_ACCESS) { - err = arm_spe__synth_mem_sample(speq, spe->l1d_access_id); + data_src = arm_spe__synth_data_source(record, + ARM_SPE_L1D_ACCESS); + + err = arm_spe__synth_mem_sample(speq, spe->l1d_access_id, + data_src); if (err) return err; } @@ -315,13 +369,21 @@ static int arm_spe_sample(struct arm_spe_queue *speq) if (spe->sample_llc) { if (record->type & ARM_SPE_LLC_MISS) { - err = arm_spe__synth_mem_sample(speq, spe->llc_miss_id); + data_src = arm_spe__synth_data_source(record, + ARM_SPE_LLC_MISS); + + err = arm_spe__synth_mem_sample(speq, spe->llc_miss_id, + data_src); if (err) return err; } if (record->type & ARM_SPE_LLC_ACCESS) { - err = arm_spe__synth_mem_sample(speq, spe->llc_access_id); + data_src = arm_spe__synth_data_source(record, + ARM_SPE_LLC_ACCESS); + + err = arm_spe__synth_mem_sample(speq, spe->llc_access_id, + data_src); if (err) return err; } @@ -329,13 +391,19 @@ static int arm_spe_sample(struct arm_spe_queue *speq) if (spe->sample_tlb) { if (record->type & ARM_SPE_TLB_MISS) { - err = arm_spe__synth_mem_sample(speq, spe->tlb_miss_id); + data_src = arm_spe__synth_data_source(record, + ARM_SPE_TLB_MISS); + err = arm_spe__synth_mem_sample(speq, spe->tlb_miss_id, + data_src); if (err) return err; } if (record->type & ARM_SPE_TLB_ACCESS) { - err = arm_spe__synth_mem_sample(speq, spe->tlb_access_id); + data_src = arm_spe__synth_data_source(record, + ARM_SPE_TLB_ACCESS); + err = arm_spe__synth_mem_sample(speq, spe->tlb_access_id, + data_src); if (err) return err; } @@ -349,7 +417,10 @@ static int arm_spe_sample(struct arm_spe_queue *speq) if (spe->sample_remote_access && (record->type & ARM_SPE_REMOTE_ACCESS)) { - err = arm_spe__synth_mem_sample(speq, spe->remote_access_id); + data_src = arm_spe__synth_data_source(record, + ARM_SPE_REMOTE_ACCESS); + err = arm_spe__synth_mem_sample(speq, spe->remote_access_id, + data_src); if (err) return err; } -- 2.17.1