From: kernel test robot <lkp@intel.com>
To: Wyatt Wood <wyatt.wood@amd.com>
Cc: kbuild-all@lists.01.org, linux-kernel@vger.kernel.org,
Alex Deucher <alexander.deucher@amd.com>,
Anthony Koo <Anthony.Koo@amd.com>
Subject: drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c:228:16-21: WARNING: conversion to bool not needed here
Date: Thu, 13 Aug 2020 17:36:04 +0800 [thread overview]
Message-ID: <202008131751.AIorNiMf%lkp@intel.com> (raw)
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tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: dc06fe51d26efc100ac74121607c01a454867c91
commit: bccbf13dadbe33452e312d828332cb9d2b553f7f drm/amd/display: Various fixes for PSR on DMCUB
date: 4 months ago
config: i386-randconfig-c001-20200813 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
coccinelle warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c:228:16-21: WARNING: conversion to bool not needed here
vim +228 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
157
158 /**
159 * Setup PSR by programming phy registers and sending psr hw context values to firmware.
160 */
161 static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
162 struct dc_link *link,
163 struct psr_context *psr_context)
164 {
165 union dmub_rb_cmd cmd;
166 struct dc_context *dc = dmub->ctx;
167 struct dmub_cmd_psr_copy_settings_data *copy_settings_data
168 = &cmd.psr_copy_settings.psr_copy_settings_data;
169 struct pipe_ctx *pipe_ctx = NULL;
170 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;
171 int i = 0;
172
173 for (i = 0; i < MAX_PIPES; i++) {
174 if (res_ctx->pipe_ctx[i].stream &&
175 res_ctx->pipe_ctx[i].stream->link == link &&
176 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {
177 pipe_ctx = &res_ctx->pipe_ctx[i];
178 break;
179 }
180 }
181
182 if (!pipe_ctx)
183 return false;
184
185 // First, set the psr version
186 if (!dmub_psr_set_version(dmub, pipe_ctx->stream))
187 return false;
188
189 // Program DP DPHY fast training registers
190 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
191 psr_context->psrExitLinkTrainingRequired);
192
193 // Program DP_SEC_CNTL1 register to set transmission GPS0 line num and priority to high
194 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
195 psr_context->sdpTransmitLineNumDeadline);
196
197 cmd.psr_copy_settings.header.type = DMUB_CMD__PSR;
198 cmd.psr_copy_settings.header.sub_type = DMUB_CMD__PSR_COPY_SETTINGS;
199 cmd.psr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_psr_copy_settings_data);
200
201 // Hw insts
202 copy_settings_data->dpphy_inst = psr_context->transmitterId;
203 copy_settings_data->aux_inst = psr_context->channel;
204 copy_settings_data->digfe_inst = psr_context->engineId;
205 copy_settings_data->digbe_inst = psr_context->transmitterId;
206
207 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
208
209 if (pipe_ctx->plane_res.dpp)
210 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
211 else
212 copy_settings_data->dpp_inst = 0;
213 if (pipe_ctx->stream_res.opp)
214 copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst;
215 else
216 copy_settings_data->opp_inst = 0;
217 if (pipe_ctx->stream_res.tg)
218 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst;
219 else
220 copy_settings_data->otg_inst = 0;
221
222 // Misc
223 copy_settings_data->psr_level = psr_context->psr_level.u32all;
224 copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations;
225 copy_settings_data->frame_delay = psr_context->frame_delay;
226 copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq;
227 copy_settings_data->debug.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR ?
> 228 true : false;
229
230 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.psr_copy_settings.header);
231 dc_dmub_srv_cmd_execute(dc->dmub_srv);
232 dc_dmub_srv_wait_idle(dc->dmub_srv);
233
234 return true;
235 }
236
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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