From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B47B5C433DF for ; Mon, 17 Aug 2020 17:27:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8DCA920657 for ; Mon, 17 Aug 2020 17:27:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="L2NQEIbv" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389767AbgHQRWA (ORCPT ); Mon, 17 Aug 2020 13:22:00 -0400 Received: from mail29.static.mailgun.info ([104.130.122.29]:38825 "EHLO mail29.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388646AbgHQQ0Z (ORCPT ); Mon, 17 Aug 2020 12:26:25 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1597681584; h=In-Reply-To: Content-Type: MIME-Version: References: Message-ID: Subject: Cc: To: From: Date: Sender; bh=3AJR1rabANV+5oYOKdD6QLeJhKliqDUS2dV6N7xL9LU=; b=L2NQEIbvimy8hZs6KUTHyT2QCOWrMbyc/hrTQZ3LuC0TheiGQwMn/POpWl7Eui2q5SrKRRcI 8gyMchodfrN+SGPsiURj1HPvC8p2nMsJl3VNaiRk2XkGXRdoPIsllXWI7UXXJX3xJBgtpnoN lMIJGHuPkQ7IvEdbgJ0gwJm8Ed4= X-Mailgun-Sending-Ip: 104.130.122.29 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n09.prod.us-east-1.postgun.com with SMTP id 5f3aaf9cba4c2cd367bbae48 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Mon, 17 Aug 2020 16:26:04 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 9543FC43387; Mon, 17 Aug 2020 16:26:03 +0000 (UTC) Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3201BC433C6; Mon, 17 Aug 2020 16:26:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3201BC433C6 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org Date: Mon, 17 Aug 2020 10:25:57 -0600 From: Jordan Crouse To: Rob Clark Cc: dri-devel@lists.freedesktop.org, Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Bjorn Andersson , Jonathan Marek , Brian Masney , Takashi Iwai , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list Subject: Re: [PATCH] drm/msm/adreno: fix updating ring fence Message-ID: <20200817162556.GD3221@jcrouse1-lnx.qualcomm.com> Mail-Followup-To: Rob Clark , dri-devel@lists.freedesktop.org, Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Bjorn Andersson , Jonathan Marek , Brian Masney , Takashi Iwai , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list References: <20200813000311.708728-1-robdclark@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200813000311.708728-1-robdclark@gmail.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 12, 2020 at 05:03:09PM -0700, Rob Clark wrote: > From: Rob Clark > > We need to set it to the most recent completed fence, not the most > recent submitted. Otherwise we have races where we think we can retire > submits that the GPU is not finished with, if the GPU doesn't manage to > overwrite the seqno before we look at it. > > This can show up with hang recovery if one of the submits after the > crashing submit also hangs after it is replayed. Reviewed-by: Jordan Crouse > Fixes: f97decac5f4c ("drm/msm: Support multiple ringbuffers") > Signed-off-by: Rob Clark > --- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > index f9e3badf2fca..34e6242c1767 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > @@ -405,7 +405,7 @@ int adreno_hw_init(struct msm_gpu *gpu) > ring->next = ring->start; > > /* reset completed fence seqno: */ > - ring->memptrs->fence = ring->seqno; > + ring->memptrs->fence = ring->fctx->completed_fence; > ring->memptrs->rptr = 0; > } > > -- > 2.26.2 > -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project