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[198.48.202.89]) by smtp.gmail.com with ESMTPSA id j16sm17335953qke.87.2020.08.17.09.32.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Aug 2020 09:32:13 -0700 (PDT) From: Liam Beguin To: liambeguin@gmail.com, kishon@ti.com, vkoul@kernel.org Cc: linux-kernel@vger.kernel.org Subject: [PATCH v3 1/1] phy: tusb1210: use bitmasks to set VENDOR_SPECIFIC2 Date: Mon, 17 Aug 2020 12:31:52 -0400 Message-Id: <20200817163152.13468-1-liambeguin@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Liam Beguin Start by reading the content of the VENDOR_SPECIFIC2 register and update each bit field based on device properties when defined. The use of bit masks prevents fields from overriding each other and enables users to clear bits which are set by default, like datapolarity in this instance. Signed-off-by: Liam Beguin --- Changes since v1: - use set_mask_bits Changes since v2: - fix missing bit shift dropped in v2 - rebase on 5.9-rc1 drivers/phy/ti/phy-tusb1210.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/phy/ti/phy-tusb1210.c b/drivers/phy/ti/phy-tusb1210.c index d8d0cc11d187..358842b5790f 100644 --- a/drivers/phy/ti/phy-tusb1210.c +++ b/drivers/phy/ti/phy-tusb1210.c @@ -14,8 +14,11 @@ #define TUSB1210_VENDOR_SPECIFIC2 0x80 #define TUSB1210_VENDOR_SPECIFIC2_IHSTX_SHIFT 0 +#define TUSB1210_VENDOR_SPECIFIC2_IHSTX_MASK GENMASK(3, 0) #define TUSB1210_VENDOR_SPECIFIC2_ZHSDRV_SHIFT 4 +#define TUSB1210_VENDOR_SPECIFIC2_ZHSDRV_MASK GENMASK(5, 4) #define TUSB1210_VENDOR_SPECIFIC2_DP_SHIFT 6 +#define TUSB1210_VENDOR_SPECIFIC2_DP_MASK BIT(6) struct tusb1210 { struct ulpi *ulpi; @@ -118,23 +121,27 @@ static int tusb1210_probe(struct ulpi *ulpi) * diagram optimization and DP/DM swap. */ + reg = ulpi_read(ulpi, TUSB1210_VENDOR_SPECIFIC2); + /* High speed output drive strength configuration */ - device_property_read_u8(&ulpi->dev, "ihstx", &val); - reg = val << TUSB1210_VENDOR_SPECIFIC2_IHSTX_SHIFT; + if (!device_property_read_u8(&ulpi->dev, "ihstx", &val)) + reg = set_mask_bits(®, TUSB1210_VENDOR_SPECIFIC2_IHSTX_MASK, + val << TUSB1210_VENDOR_SPECIFIC2_IHSTX_SHIFT); /* High speed output impedance configuration */ - device_property_read_u8(&ulpi->dev, "zhsdrv", &val); - reg |= val << TUSB1210_VENDOR_SPECIFIC2_ZHSDRV_SHIFT; + if (!device_property_read_u8(&ulpi->dev, "zhsdrv", &val)) + reg = set_mask_bits(®, TUSB1210_VENDOR_SPECIFIC2_ZHSDRV_MASK, + val << TUSB1210_VENDOR_SPECIFIC2_ZHSDRV_SHIFT); /* DP/DM swap control */ - device_property_read_u8(&ulpi->dev, "datapolarity", &val); - reg |= val << TUSB1210_VENDOR_SPECIFIC2_DP_SHIFT; - - if (reg) { - ulpi_write(ulpi, TUSB1210_VENDOR_SPECIFIC2, reg); - tusb->vendor_specific2 = reg; + if (!device_property_read_u8(&ulpi->dev, "datapolarity", &val)) { + reg = set_mask_bits(®, TUSB1210_VENDOR_SPECIFIC2_DP_MASK, + val << TUSB1210_VENDOR_SPECIFIC2_DP_SHIFT); } + ulpi_write(ulpi, TUSB1210_VENDOR_SPECIFIC2, reg); + tusb->vendor_specific2 = reg; + tusb->phy = ulpi_phy_create(ulpi, &phy_ops); if (IS_ERR(tusb->phy)) return PTR_ERR(tusb->phy); base-commit: 9123e3a74ec7b934a4a099e98af6a61c2f80bbf5 -- 2.27.0