From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91522C433E3 for ; Mon, 17 Aug 2020 17:33:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 68B362063A for ; Mon, 17 Aug 2020 17:33:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="PR5Mnv9q" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389100AbgHQRdh (ORCPT ); Mon, 17 Aug 2020 13:33:37 -0400 Received: from mail29.static.mailgun.info ([104.130.122.29]:48097 "EHLO mail29.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729092AbgHQQxY (ORCPT ); Mon, 17 Aug 2020 12:53:24 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1597683203; h=In-Reply-To: Content-Type: MIME-Version: References: Message-ID: Subject: Cc: To: From: Date: Sender; bh=vvIj8nL35Cjq14NalPJcQsLYy6Oeb6O5Y2EHRW7KxX4=; b=PR5Mnv9qxlLkEC95ozeKIunl4YYUH/xQ1FLau/jxA2r3bcG+cphRi/WM1+rSPYyXZEz1GuvY pytrxtAiNM3PMIi2fQVAK289Tt9eP5t+U7ensV3EqpBxUsiKw/sO5A0r/ApwZLaCmmtSM4eH 6Y63BTdGA973XZFZIDltwQlsDfQ= X-Mailgun-Sending-Ip: 104.130.122.29 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n08.prod.us-west-2.postgun.com with SMTP id 5f3ab5f203528d4024fec304 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Mon, 17 Aug 2020 16:53:06 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id AF514C433A0; Mon, 17 Aug 2020 16:53:05 +0000 (UTC) Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1C653C433C6; Mon, 17 Aug 2020 16:53:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1C653C433C6 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org Date: Mon, 17 Aug 2020 10:52:59 -0600 From: Jordan Crouse To: Rob Clark Cc: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Rob Clark , Sai Prakash Ranjan , open list , Will Deacon , Joerg Roedel , Robin Murphy , Bjorn Andersson , Sibi Sankar , Vivek Gautam , Stephen Boyd , freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Subject: Re: [Freedreno] [PATCH 05/19] iommu: add private interface for adreno-smmu Message-ID: <20200817165259.GH3221@jcrouse1-lnx.qualcomm.com> Mail-Followup-To: Rob Clark , dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Rob Clark , Sai Prakash Ranjan , open list , Will Deacon , Joerg Roedel , Robin Murphy , Bjorn Andersson , Sibi Sankar , Vivek Gautam , Stephen Boyd , freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-6-robdclark@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200814024114.1177553-6-robdclark@gmail.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Aug 13, 2020 at 07:41:00PM -0700, Rob Clark wrote: > From: Rob Clark > > This interface will be used for drm/msm to coordinate with the > qcom_adreno_smmu_impl to enable/disable TTBR0 translation. > > Once TTBR0 translation is enabled, the GPU's CP (Command Processor) > will directly switch TTBR0 pgtables (and do the necessary TLB inv) > synchronized to the GPU's operation. But help from the SMMU driver > is needed to initially bootstrap TTBR0 translation, which cannot be > done from the GPU. > > Since this is a very special case, a private interface is used to > avoid adding highly driver specific things to the public iommu > interface. > Reviewed-by: Jordan Crouse > Signed-off-by: Rob Clark > --- > include/linux/adreno-smmu-priv.h | 36 ++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > create mode 100644 include/linux/adreno-smmu-priv.h > > diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h > new file mode 100644 > index 000000000000..a889f28afb42 > --- /dev/null > +++ b/include/linux/adreno-smmu-priv.h > @@ -0,0 +1,36 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2020 Google, Inc > + */ > + > +#ifndef __ADRENO_SMMU_PRIV_H > +#define __ADRENO_SMMU_PRIV_H > + > +#include > + > +/** > + * struct adreno_smmu_priv - private interface between adreno-smmu and GPU > + * > + * @cookie: An opque token provided by adreno-smmu and passed > + * back into the callbacks > + * @get_ttbr1_cfg: Get the TTBR1 config for the GPUs context-bank > + * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A > + * NULL config disables TTBR0 translation, otherwise > + * TTBR0 translation is enabled with the specified cfg > + * > + * The GPU driver (drm/msm) and adreno-smmu work together for controlling > + * the GPU's SMMU instance. This is by necessity, as the GPU is directly > + * updating the SMMU for context switches, while on the other hand we do > + * not want to duplicate all of the initial setup logic from arm-smmu. > + * > + * This private interface is used for the two drivers to coordinate. The > + * cookie and callback functions are populated when the GPU driver attaches > + * it's domain. > + */ > +struct adreno_smmu_priv { > + const void *cookie; > + const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); > + int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); > +}; > + > +#endif /* __ADRENO_SMMU_PRIV_H */ > \ No newline at end of file > -- > 2.26.2 > > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project