From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40DE5C433E3 for ; Thu, 20 Aug 2020 00:04:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 15F7F207FB for ; Thu, 20 Aug 2020 00:04:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597881862; bh=6aHggL1RkTAzBEHv4FvfQ9+Mk3/6PJyf2EJjPbmIUQE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=RLp0BO7cRlUh7CU0FcTgIzDpSWNeGBqo2qNB6QIFSeDMh+ztmVT724xt2pXOwSUWl vYNoCvUaQHfE+SO5Xbp3dwKBPX61QmE7iWY/JV0g2rtwgT1gAHcK+PMt3PNO3ZCCtO B/niLWgYU/aA8zLO/ZZ7QdWesW+n6/Kw3wpyD3Cs= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728458AbgHTAET (ORCPT ); Wed, 19 Aug 2020 20:04:19 -0400 Received: from mail.kernel.org ([198.145.29.99]:34492 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728423AbgHTAEM (ORCPT ); Wed, 19 Aug 2020 20:04:12 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id AD3C7208E4; Thu, 20 Aug 2020 00:04:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597881852; bh=6aHggL1RkTAzBEHv4FvfQ9+Mk3/6PJyf2EJjPbmIUQE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SiSS5mPYZR6/l1bLpcOJc+6qvXxOb4m22vuNXD2GMyDa8mVXE7hoU40K6H87jaXFc 4lA2nGY8P8v49YQthk1oecgW4kVGrDOkgO7xuN3jNZfAe3gZZS0RZc0AMPi3gY2EXc kALgFi9jbSXr85fAo09VICwB8NooTXpgfGeo3P9Y= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Greg Ungerer , Sasha Levin , linux-m68k@lists.linux-m68k.org Subject: [PATCH AUTOSEL 4.4 04/10] m68knommu: fix overwriting of bits in ColdFire V3 cache control Date: Wed, 19 Aug 2020 20:04:00 -0400 Message-Id: <20200820000406.216050-4-sashal@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200820000406.216050-1-sashal@kernel.org> References: <20200820000406.216050-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Greg Ungerer [ Upstream commit bdee0e793cea10c516ff48bf3ebb4ef1820a116b ] The Cache Control Register (CACR) of the ColdFire V3 has bits that control high level caching functions, and also enable/disable the use of the alternate stack pointer register (the EUSP bit) to provide separate supervisor and user stack pointer registers. The code as it is today will blindly clear the EUSP bit on cache actions like invalidation. So it is broken for this case - and that will result in failed booting (interrupt entry and exit processing will be completely hosed). This only affects ColdFire V3 parts that support the alternate stack register (like the 5329 for example) - generally speaking new parts do, older parts don't. It has no impact on ColdFire V3 parts with the single stack pointer, like the 5307 for example. Fix the cache bit defines used, so they maintain the EUSP bit when carrying out cache actions through the CACR register. Signed-off-by: Greg Ungerer Signed-off-by: Sasha Levin --- arch/m68k/include/asm/m53xxacr.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h index 3177ce8331d69..baee0c77b9818 100644 --- a/arch/m68k/include/asm/m53xxacr.h +++ b/arch/m68k/include/asm/m53xxacr.h @@ -88,9 +88,9 @@ * coherency though in all cases. And for copyback caches we will need * to push cached data as well. */ -#define CACHE_INIT CACR_CINVA -#define CACHE_INVALIDATE CACR_CINVA -#define CACHE_INVALIDATED CACR_CINVA +#define CACHE_INIT (CACHE_MODE + CACR_CINVA - CACR_EC) +#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINVA) +#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINVA) #define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ (0x000f0000) + \ -- 2.25.1