From: Andy Shevchenko <andriy.shevchenko@intel.com>
To: Rahul Tanwar <rahul.tanwar@linux.intel.com>
Cc: u.kleine-koenig@pengutronix.de, linux-pwm@vger.kernel.org,
lee.jones@linaro.org, thierry.reding@gmail.com,
p.zabel@pengutronix.de, robh+dt@kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
songjun.Wu@intel.com, cheol.yong.kim@intel.com,
qi-ming.wu@intel.com, rahul.tanwar.linux@gmail.com,
rtanwar@maxlinear.com
Subject: Re: [PATCH v8 2/2] Add PWM fan controller driver for LGM SoC
Date: Thu, 20 Aug 2020 13:52:55 +0300 [thread overview]
Message-ID: <20200820105255.GB1891694@smile.fi.intel.com> (raw)
In-Reply-To: <b6d0a65625a2bc231c649c970c0a1af1ff3a5dd5.1597898872.git.rahul.tanwar@linux.intel.com>
On Thu, Aug 20, 2020 at 12:50:46PM +0800, Rahul Tanwar wrote:
> Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
> This PWM controller does not have any other consumer, it is a
> dedicated PWM controller for fan attached to the system. Add
> driver for this PWM fan controller.
...
> +config PWM_INTEL_LGM
> + tristate "Intel LGM PWM support"
> + depends on OF && HAS_IOMEM
> + depends on X86 || COMPILE_TEST
For better test coverage you may rewrite this
depends on HAS_IOMEM
depends on (OF && X86) || COMPILE_TEST
> + select REGMAP_MMIO
> + help
> + Generic PWM fan controller driver for LGM SoC.
> +
> + To compile this driver as a module, choose M here: the module
> + will be called pwm-intel-lgm.
...
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
This should be mod_devicetable.h.
> +#include <linux/pwm.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
...
> +#define LGM_PWM_PERIOD_2WIRE_NSECS 40000000
NSECS -> NS
40000000 -> (40 * NSEC_PER_MSEC)
...
> + if (state->polarity != PWM_POLARITY_NORMAL ||
> + state->period < pc->period)
It can be one line.
> + return -EINVAL;
...
> + if (!state->enabled) {
> + ret = lgm_pwm_enable(chip, 0);
> + return ret;
What is the point?
> + }
...
> + ret = lgm_pwm_enable(chip, 1);
> +
> + return ret;
Ditto.
...
> + state->duty_cycle = DIV_ROUND_UP(duty * pc->period,
> + LGM_PWM_MAX_DUTY_CYCLE);
One line?
...
> + struct lgm_pwm_chip *pc;
> + struct device *dev = &pdev->dev;
Use reversed xmas tree order.
> + void __iomem *io_base;
> + int ret;
...
> + pc->regmap = devm_regmap_init_mmio(dev, io_base, &lgm_pwm_regmap_config);
> + if (IS_ERR(pc->regmap)) {
> + ret = PTR_ERR(pc->regmap);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "failed to init register map: %pe\n",
> + pc->regmap);
> + return ret;
dev_err_probe()
> + }
...
> + pc->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(pc->clk)) {
> + ret = PTR_ERR(pc->clk);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "failed to get clock: %pe\n", pc->clk);
> + return ret;
Ditto.
> + }
> +
> + pc->rst = devm_reset_control_get_exclusive(dev, NULL);
> + if (IS_ERR(pc->rst)) {
> + ret = PTR_ERR(pc->rst);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "failed to get reset control: %pe\n",
> + pc->rst);
> + return ret;
Ditto.
> + }
> +
> + ret = reset_control_deassert(pc->rst);
> + if (ret) {
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "cannot deassert reset control: %pe\n",
> + ERR_PTR(ret));
> + return ret;
Ditto.
> + }
...
> + ret = clk_prepare_enable(pc->clk);
Wrap it with devm_add_action_or_reset(). Same for reset_control_deassert().
You probably can even put them under one function.
> + if (ret) {
> + dev_err(dev, "failed to enable clock\n");
> + reset_control_assert(pc->rst);
> + return ret;
> + }
...
> + ret = pwmchip_add(&pc->chip);
> + if (ret < 0) {
Does ' < 0' have any meaning?
> + dev_err(dev, "failed to add PWM chip: %pe\n", ERR_PTR(ret));
> + clk_disable_unprepare(pc->clk);
> + reset_control_assert(pc->rst);
> + return ret;
> + }
...
> + ret = pwmchip_remove(&pc->chip);
> + if (ret < 0)
Ditto.
> + return ret;
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2020-08-20 10:53 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-20 4:50 [PATCH v8 0/2] pwm: intel: Add PWM driver for a new SoC Rahul Tanwar
2020-08-20 4:50 ` [PATCH v8 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC Rahul Tanwar
2020-08-20 4:50 ` [PATCH v8 2/2] Add PWM fan controller driver for " Rahul Tanwar
2020-08-20 10:52 ` Andy Shevchenko [this message]
2020-08-21 6:07 ` Tanwar, Rahul
2020-08-21 8:23 ` Andy Shevchenko
2020-08-21 9:14 ` Tanwar, Rahul
2020-08-21 10:52 ` Andy Shevchenko
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200820105255.GB1891694@smile.fi.intel.com \
--to=andriy.shevchenko@intel.com \
--cc=cheol.yong.kim@intel.com \
--cc=devicetree@vger.kernel.org \
--cc=lee.jones@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pwm@vger.kernel.org \
--cc=p.zabel@pengutronix.de \
--cc=qi-ming.wu@intel.com \
--cc=rahul.tanwar.linux@gmail.com \
--cc=rahul.tanwar@linux.intel.com \
--cc=robh+dt@kernel.org \
--cc=rtanwar@maxlinear.com \
--cc=songjun.Wu@intel.com \
--cc=thierry.reding@gmail.com \
--cc=u.kleine-koenig@pengutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®