From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2326C433E2 for ; Thu, 3 Sep 2020 17:14:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AF62E20775 for ; Thu, 3 Sep 2020 17:14:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="RNLxKJPI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729153AbgICROi (ORCPT ); Thu, 3 Sep 2020 13:14:38 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:49104 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728965AbgICRNx (ORCPT ); Thu, 3 Sep 2020 13:13:53 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 083HDcTT042723; Thu, 3 Sep 2020 12:13:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1599153218; bh=AE4yNpb4R97gKAzfv6K8ax76ClT45diBmtWHH8vhJVw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RNLxKJPIqrebo03HCgOlMWrpS1cX5Byl2TEoBlHRD2qqh78TD3QtSjLOzfSmfXw0D 3c9ZpoAqA6gTFzcf/5X4CM8te9KuSodMqWYrf1V6Sq2OZWeBoMrGZ3KW/eRazE5jfl DLfSgNYEM++u9P44OPCXD7THWRxE580CEdgjdOJM= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 083HDcep021707 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 3 Sep 2020 12:13:38 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 3 Sep 2020 12:13:38 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 3 Sep 2020 12:13:38 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 083HDDQ2088669; Thu, 3 Sep 2020 12:13:35 -0500 From: Pratyush Yadav To: Tudor Ambarus , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , "open list:SPI NOR SUBSYSTEM" , open list CC: Pratyush Yadav , Sekhar Nori , Boris Brezillon Subject: [PATCH v12 07/14] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode Date: Thu, 3 Sep 2020 22:43:06 +0530 Message-ID: <20200903171313.18741-8-p.yadav@ti.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200903171313.18741-1-p.yadav@ti.com> References: <20200903171313.18741-1-p.yadav@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some controllers, like the cadence qspi controller, have trouble reading only 1 byte in DTR mode. So, do 2 byte reads for SR and FSR commands in DTR mode, and then discard the second byte. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 83ad58508855..429151dfcddf 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -364,7 +364,7 @@ int spi_nor_write_disable(struct spi_nor *nor) * spi_nor_read_sr() - Read the Status Register. * @nor: pointer to 'struct spi_nor'. * @sr: pointer to a DMA-able buffer where the value of the - * Status Register will be written. + * Status Register will be written. Should be at least 2 bytes. * * Return: 0 on success, -errno otherwise. */ @@ -382,6 +382,11 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) if (spi_nor_protocol_is_dtr(nor->reg_proto)) { op.addr.nbytes = nor->params->rdsr_addr_nbytes; op.dummy.nbytes = nor->params->rdsr_dummy; + /* + * We don't want to read only one byte in DTR mode. So, + * read 2 and then discard the second byte. + */ + op.data.nbytes = 2; } spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); @@ -400,7 +405,8 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) * spi_nor_read_fsr() - Read the Flag Status Register. * @nor: pointer to 'struct spi_nor' * @fsr: pointer to a DMA-able buffer where the value of the - * Flag Status Register will be written. + * Flag Status Register will be written. Should be at least 2 + * bytes. * * Return: 0 on success, -errno otherwise. */ @@ -418,6 +424,11 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr) if (spi_nor_protocol_is_dtr(nor->reg_proto)) { op.addr.nbytes = nor->params->rdsr_addr_nbytes; op.dummy.nbytes = nor->params->rdsr_dummy; + /* + * We don't want to read only one byte in DTR mode. So, + * read 2 and then discard the second byte. + */ + op.data.nbytes = 2; } spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); -- 2.25.0