From: "Guido Günther" <agx@sigxcpu.org>
To: "Robert Chiras (OSS)" <robert.chiras@oss.nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Andrzej Hajda <a.hajda@samsung.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
Jonas Karlman <jonas@kwiboo.se>,
Jernej Skrabec <jernej.skrabec@siol.net>,
Sam Ravnborg <sam@ravnborg.org>,
Fabio Estevam <festevam@gmail.com>,
Ondrej Jirman <megous@megous.com>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-imx@nxp.com
Subject: Re: [PATCH 0/5] Add new features to nwl-dsi driver
Date: Fri, 4 Sep 2020 19:08:02 +0200 [thread overview]
Message-ID: <20200904170802.GD755526@bogon.m.sigxcpu.org> (raw)
In-Reply-To: <1598613212-1113-1-git-send-email-robert.chiras@oss.nxp.com>
Hi Robert,
On Fri, Aug 28, 2020 at 02:13:27PM +0300, Robert Chiras (OSS) wrote:
> From: Robert Chiras <robert.chiras@nxp.com>
>
> This patch-set adds the new following features to the nwl-dsi bridge driver:
>
> 1. Control Video PLL from nwl-dsi driver
>
> Add support for the Video PLL into the nwl-dsi driver, in order
> to better control it's rate, depending on the requested video mode.
> Controlling the Video PLL from nwl-dsi is usefull, since it both drives the DC
> pixel-clock and DPHY phy_ref clock.
> On i.MX8MQ, the DC can be either DCSS or LCDIF.
>
> 2. Add new property to nwl-dsi: clock-drop-level
>
> This new property is usefull in order to use DSI panels with the nwl-dsi
> driver which require a higher overhead to the pixel-clock.
> For example, the Raydium RM67191 DSI Panel works with 132M pixel-clock,
> but it needs an overhead in order to work properly. So, the actual pixel-clock
> fed into the DSI DPI interface needs to be lower than the one used ad DSI output.
> This new property addresses this matter.
>
> 3. Add support to handle both inputs for nwl-dsi: DCSS and LCDIF
Thanks. I've tested the drop-clock-level part with mxsfb on a Librem 5
devkit and it removes the slight flickering we've seen before (and which
could be worked around by reducing the input pixel clock so 1 and 3 are
Tested-by: Guido Günther <agx@sigxcpu.org>
I've have added some comments to the individual patches and try to get
around to check out the DCSS part too.
Cheers,
-- Guido
>
> Laurentiu Palcu (1):
> drm/bridge: nwl-dsi: add support for DCSS
>
> Robert Chiras (4):
> drm/bridge: nwl-dsi: Add support for video_pll
> dt-bindings: display/bridge: nwl-dsi: Document video_pll clock
> drm/bridge: nwl-dsi: Add support for clock-drop-level
> dt-bindings: display/bridge: nwl-dsi: Document fsl,clock-drop-level
> property
>
> .../bindings/display/bridge/nwl-dsi.yaml | 7 +
> drivers/gpu/drm/bridge/nwl-dsi.c | 338 ++++++++++++++++++++-
> 2 files changed, 336 insertions(+), 9 deletions(-)
>
> --
> 2.7.4
>
prev parent reply other threads:[~2020-09-04 18:10 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-28 11:13 Robert Chiras (OSS)
2020-08-28 11:13 ` [PATCH 1/5] drm/bridge: nwl-dsi: Add support for video_pll Robert Chiras (OSS)
2020-09-04 17:04 ` Guido Günther
2020-08-28 11:13 ` [PATCH 2/5] dt-bindings: display/bridge: nwl-dsi: Document video_pll clock Robert Chiras (OSS)
2020-08-28 21:40 ` Rob Herring
2020-08-28 11:13 ` [PATCH 3/5] drm/bridge: nwl-dsi: Add support for clock-drop-level Robert Chiras (OSS)
2020-09-06 10:28 ` Guido Günther
2020-08-28 11:13 ` [PATCH 4/5] dt-bindings: display/bridge: nwl-dsi: Document fsl,clock-drop-level property Robert Chiras (OSS)
2020-09-04 17:05 ` Guido Günther
2020-09-05 16:07 ` Laurent Pinchart
2020-09-09 20:43 ` Rob Herring
2020-08-28 11:13 ` [PATCH 5/5] drm/bridge: nwl-dsi: add support for DCSS Robert Chiras (OSS)
2020-09-04 17:05 ` Guido Günther
2020-09-04 17:08 ` Guido Günther [this message]
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