From: Hsin-Yi Wang <hsinyi@chromium.org>
To: linux-mediatek@lists.infradead.org
Cc: Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Enric Balletbo i Serra <enric.balletbo@collabora.com>
Subject: [PATCH v2 2/2] arm64: dts: mt8183: Set uart to mmio32 iotype
Date: Thu, 10 Sep 2020 16:43:04 +0800 [thread overview]
Message-ID: <20200910084304.3429494-2-hsinyi@chromium.org> (raw)
In-Reply-To: <20200910084304.3429494-1-hsinyi@chromium.org>
Set uart iotype to mmio32 to make earlycon work with stdout-path.
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 102105871db25..0bda97f912789 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -374,6 +374,8 @@ uart0: serial@11002000 {
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
+ reg-io-width = <4>;
+ reg-shift = <2>;
status = "disabled";
};
@@ -384,6 +386,8 @@ uart1: serial@11003000 {
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
clock-names = "baud", "bus";
+ reg-io-width = <4>;
+ reg-shift = <2>;
status = "disabled";
};
@@ -394,6 +398,8 @@ uart2: serial@11004000 {
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
clock-names = "baud", "bus";
+ reg-io-width = <4>;
+ reg-shift = <2>;
status = "disabled";
};
--
2.28.0.526.ge36021eeef-goog
next prev parent reply other threads:[~2020-09-10 8:45 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-10 8:43 [PATCH v2 1/2] arm64: dts: mt8173: " Hsin-Yi Wang
2020-09-10 8:43 ` Hsin-Yi Wang [this message]
2020-09-10 10:25 ` Matthias Brugger
2020-09-10 13:40 ` Hsin-Yi Wang
2020-09-11 9:43 ` Hsin-Yi Wang
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