From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9E96C43461 for ; Fri, 11 Sep 2020 17:32:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 79B2D221E7 for ; Fri, 11 Sep 2020 17:32:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726462AbgIKRcG (ORCPT ); Fri, 11 Sep 2020 13:32:06 -0400 Received: from relay8-d.mail.gandi.net ([217.70.183.201]:37519 "EHLO relay8-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726558AbgIKRbp (ORCPT ); Fri, 11 Sep 2020 13:31:45 -0400 X-Originating-IP: 91.224.148.103 Received: from localhost.localdomain (unknown [91.224.148.103]) (Authenticated sender: miquel.raynal@bootlin.com) by relay8-d.mail.gandi.net (Postfix) with ESMTPSA id C9F351BF205; Fri, 11 Sep 2020 17:31:42 +0000 (UTC) From: Miquel Raynal To: Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai Cc: alsa-devel@alsa-project.org, , Thomas Petazzoni , Alexandre Belloni , Miquel Raynal Subject: [PATCH 1/3] ASoC: tlv320aic32x4: Ensure a minimum delay before clock stabilization Date: Fri, 11 Sep 2020 19:31:38 +0200 Message-Id: <20200911173140.29984-2-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200911173140.29984-1-miquel.raynal@bootlin.com> References: <20200911173140.29984-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As indicated in the datasheet, a 10ms delay must be observed after programming the divisors. The lack of delay prevents the codec to work properly and the playback appears extremely slow and totally un-audible on a custom sama5 based board. Signed-off-by: Miquel Raynal --- sound/soc/codecs/tlv320aic32x4-clk.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/sound/soc/codecs/tlv320aic32x4-clk.c b/sound/soc/codecs/tlv320aic32x4-clk.c index 156c153c12ab..2f78e6820c75 100644 --- a/sound/soc/codecs/tlv320aic32x4-clk.c +++ b/sound/soc/codecs/tlv320aic32x4-clk.c @@ -230,7 +230,14 @@ static int clk_aic32x4_pll_set_rate(struct clk_hw *hw, if (ret < 0) return -EINVAL; - return clk_aic32x4_pll_set_muldiv(pll, &settings); + ret = clk_aic32x4_pll_set_muldiv(pll, &settings); + if (ret) + return ret; + + /* 10ms is the delay to wait before the clocks are stable */ + msleep(10); + + return 0; } static int clk_aic32x4_pll_set_parent(struct clk_hw *hw, u8 index) -- 2.20.1