From: Krish Sadhukhan <krish.sadhukhan@oracle.com>
To: kvm@vger.kernel.org
Cc: pbonzini@redhat.com, jmattson@google.com, tglx@linutronix.de,
mingo@redhat.com, bp@alien8.de, x86@kernel.org,
sean.j.christopherson@intel.com, vkuznets@redhat.com,
wanpengli@tencent.com, joro@8bytes.org,
dave.hansen@linux.intel.com, luto@kernel.org,
peterz@infradead.org, linux-kernel@vger.kernel.org,
hpa@zytor.com
Subject: [PATCH 3/4 v3] x86: AMD: Don't flush cache if hardware enforces cache coherency across encryption domnains
Date: Fri, 11 Sep 2020 19:26:00 +0000 [thread overview]
Message-ID: <20200911192601.9591-4-krish.sadhukhan@oracle.com> (raw)
In-Reply-To: <20200911192601.9591-1-krish.sadhukhan@oracle.com>
In some hardware implementations, coherency between the encrypted and
unencrypted mappings of the same physical page is enforced. In such a system,
it is not required for software to flush the page from all CPU caches in the
system prior to changing the value of the C-bit for the page.
Suggested-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
---
arch/x86/mm/pat/set_memory.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c
index d1b2a889f035..78d5511c5edd 100644
--- a/arch/x86/mm/pat/set_memory.c
+++ b/arch/x86/mm/pat/set_memory.c
@@ -1999,7 +1999,7 @@ static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc)
/*
* Before changing the encryption attribute, we need to flush caches.
*/
- cpa_flush(&cpa, 1);
+ cpa_flush(&cpa, !this_cpu_has(X86_FEATURE_HW_CACHE_COHERENCY));
ret = __change_page_attr_set_clr(&cpa, 1);
--
2.18.4
next prev parent reply other threads:[~2020-09-11 19:29 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-11 19:25 [PATCH 0/4 v3] x86: AMD: Don't flush cache if hardware enforces cache coherency across encryption domains Krish Sadhukhan
2020-09-11 19:25 ` [PATCH 1/4 v3] x86: AMD: Replace numeric value for SME CPUID leaf with a #define Krish Sadhukhan
2020-09-11 21:21 ` Borislav Petkov
2020-09-12 6:54 ` Paolo Bonzini
2020-09-11 19:25 ` [PATCH 2/4 v3] x86: AMD: Add hardware-enforced cache coherency as a CPUID feature Krish Sadhukhan
2020-09-11 19:36 ` Dave Hansen
2020-09-11 20:10 ` Krish Sadhukhan
2020-09-11 20:58 ` Dave Hansen
2020-09-11 21:33 ` Borislav Petkov
2020-09-11 21:44 ` Tom Lendacky
2020-09-11 19:26 ` Krish Sadhukhan [this message]
2020-09-11 19:26 ` [PATCH 4/4 v3] KVM: SVM: Don't flush cache if hardware enforces cache coherency across encryption domains Krish Sadhukhan
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