From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67B4BC2D0E2 for ; Tue, 22 Sep 2020 10:12:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EFFA9239CF for ; Tue, 22 Sep 2020 10:12:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726514AbgIVKMd (ORCPT ); Tue, 22 Sep 2020 06:12:33 -0400 Received: from foss.arm.com ([217.140.110.172]:32916 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726473AbgIVKMc (ORCPT ); Tue, 22 Sep 2020 06:12:32 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E60E0D6E; Tue, 22 Sep 2020 03:12:31 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.195.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DAF253F718; Tue, 22 Sep 2020 03:12:29 -0700 (PDT) From: Andre Przywara To: Will Deacon , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Suzuki K Poulose , Leo Yan , Tan Xiaojun , James Clark , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/5] perf: arm64: Support ARMv8.3-SPE extensions Date: Tue, 22 Sep 2020 11:12:20 +0100 Message-Id: <20200922101225.183554-1-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The "ARMv8.3-SPE extensions" add some bits to SPE to cover newer architecture features, most prominently SVE. Add the new bits where needed, mostly to perf's SPE packet decoder. Cheers, Andre Andre Przywara (5): arm64: spe: Allow new bits in SPE filter register perf: arm_spe: Add new event packet bits perf: arm_spe: Add nested virt event decoding perf: arm_spe: Decode memory tagging properties perf: arm_spe: Decode SVE events arch/arm64/include/asm/sysreg.h | 2 +- .../arm-spe-decoder/arm-spe-pkt-decoder.c | 86 +++++++++++++++++-- 2 files changed, 81 insertions(+), 7 deletions(-) -- 2.17.1