From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE107C2D0E2 for ; Tue, 22 Sep 2020 21:04:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7D48723600 for ; Tue, 22 Sep 2020 21:04:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=kwiboo.se header.i=@kwiboo.se header.b="O4dYcW/n" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726770AbgIVVE6 (ORCPT ); Tue, 22 Sep 2020 17:04:58 -0400 Received: from o1.b.az.sendgrid.net ([208.117.55.133]:9024 "EHLO o1.b.az.sendgrid.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726448AbgIVVEp (ORCPT ); Tue, 22 Sep 2020 17:04:45 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=from:subject:in-reply-to:references:to:cc:content-type: content-transfer-encoding; s=001; bh=z7v+PHtCfxxSYzksa8sjIkGNZO+Cebil1muBgONTycw=; b=O4dYcW/nENsS02C/6wdnP6UatDC7VgiZ8M+Tt7huKkYZ0n+bVsKiV8SX5jVf80BAea1o aXB+l2OytQXK49EwYQS2uNeJiQkudTM39c2mLWLTYCwOUE0PlsUctIeGYSDRdaY3qR86R9 J7vcDxPMzfs/AN1AKGdTiLgkkhhHPh5iI= Received: by filterdrecv-p3las1-6f66587546-wqxvn with SMTP id filterdrecv-p3las1-6f66587546-wqxvn-20-5F6A65BD-23 2020-09-22 20:59:41.437087089 +0000 UTC m=+82864.960540649 Received: from bionic.localdomain (unknown) by ismtpd0007p1lon1.sendgrid.net (SG) with ESMTP id NnXEwi6lTwuUw91Zhyu9WA Tue, 22 Sep 2020 20:59:41.121 +0000 (UTC) From: Jonas Karlman Subject: [PATCH v3 4/6] phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg write Date: Tue, 22 Sep 2020 20:59:41 +0000 (UTC) Message-Id: <20200922205933.5540-5-jonas@kwiboo.se> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200922205933.5540-1-jonas@kwiboo.se> References: <20200108210740.28769-1-jonas@kwiboo.se> <20200922205933.5540-1-jonas@kwiboo.se> X-SG-EID: =?us-ascii?Q?TdbjyGynYnRZWhH+7lKUQJL+ZxmxpowvO2O9SQF5CwCVrYgcwUXgU5DKUU3QxA?= =?us-ascii?Q?fZekEeQsTe+RrMu3cja6a0hycbaCzZAc3bUCs33?= =?us-ascii?Q?ze14gXl2dCdHz7UDSt+smZ7Bkz6LKFaWj5FDza4?= =?us-ascii?Q?aLqhUHWjMWhAVxU9KtquBMpi2pAS2XJ3rz5dCT5?= =?us-ascii?Q?2OTcApIT17Nbp61fbPyOhwn2Mzku=2FFaHWKMJNQn?= =?us-ascii?Q?JwA6NL70jwxru+HTFyNjrFlxRROCP0n+3Z8dvYR?= =?us-ascii?Q?THpO2O5jpEtDHv+NkH7vw=3D=3D?= To: Kishon Vijay Abraham I , Heiko Stuebner Cc: Jonas Karlman , Vinod Koul , Zheng Yang , Algea Cao , Huicong Xu , linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org inno_write is used to configure 0xaa reg, that also hold the POST_PLL_POWER_DOWN bit. When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not taken into consideration. Fix this by keeping the power down bit until configuration is complete. Also reorder the reg write order for consistency. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Jonas Karlman --- drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c index 06db69c8373e..3a59a6da0440 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -1020,9 +1020,10 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); if (cfg->postdiv == 1) { - inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS); inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | RK3328_POST_PLL_PRE_DIV(cfg->prediv)); + inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS | + RK3328_POST_PLL_POWER_DOWN); } else { v = (cfg->postdiv / 2) - 1; v &= RK3328_POST_PLL_POST_DIV_MASK; @@ -1030,7 +1031,8 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | RK3328_POST_PLL_PRE_DIV(cfg->prediv)); inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE | - RK3328_POST_PLL_REFCLK_SEL_TMDS); + RK3328_POST_PLL_REFCLK_SEL_TMDS | + RK3328_POST_PLL_POWER_DOWN); } for (v = 0; v < 14; v++) -- 2.17.1