From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A819C2D0A8 for ; Wed, 23 Sep 2020 18:04:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4474D2075B for ; Wed, 23 Sep 2020 18:04:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726902AbgIWSEp (ORCPT ); Wed, 23 Sep 2020 14:04:45 -0400 Received: from mga05.intel.com ([192.55.52.43]:39920 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726785AbgIWSEY (ORCPT ); Wed, 23 Sep 2020 14:04:24 -0400 IronPort-SDR: QA7I5rYZBqrAJXHLZD7dHt/vM4Fzee02R4NarvEUN3zovh0X/iiPsbo/N1FoKb26hBDvNyvpZ6 aNrwTINZzQHg== X-IronPort-AV: E=McAfee;i="6000,8403,9753"; a="245808974" X-IronPort-AV: E=Sophos;i="5.77,293,1596524400"; d="scan'208";a="245808974" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2020 11:04:13 -0700 IronPort-SDR: yoN1458qw0Kaql42Ri4RIYaS19zPA4c9xxONmziFmsF9lHyYS4iJytIxd859/WRGx0DbMcrFjo RZPxmHsVoibw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,293,1596524400"; d="scan'208";a="322670291" Received: from sjchrist-coffee.jf.intel.com ([10.54.74.160]) by orsmga002.jf.intel.com with ESMTP; 23 Sep 2020 11:04:11 -0700 From: Sean Christopherson To: Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 10/15] KVM: VMX: Move uret MSR lookup into update_transition_efer() Date: Wed, 23 Sep 2020 11:04:04 -0700 Message-Id: <20200923180409.32255-11-sean.j.christopherson@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200923180409.32255-1-sean.j.christopherson@intel.com> References: <20200923180409.32255-1-sean.j.christopherson@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Move checking for the existence of MSR_EFER in the uret MSR array into update_transition_efer() so that the lookup and manipulation of the array in setup_msrs() occur back-to-back. This paves the way toward adding a helper to wrap the lookup and manipulation. To avoid unnecessary overhead, defer the lookup until the uret array would actually be modified in update_transition_efer(). EFER obviously exists on CPUs that support the dedicated VMCS fields for switching EFER, and EFER must exist for the guest and host EFER.NX value to diverge, i.e. there is no danger of attempting to read/write EFER when it doesn't exist. Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/vmx.c | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index ed9ce25d3807..f3192855f0fb 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -953,10 +953,11 @@ static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, m->host.val[j].value = host_val; } -static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) +static bool update_transition_efer(struct vcpu_vmx *vmx) { u64 guest_efer = vmx->vcpu.arch.efer; u64 ignore_bits = 0; + int i; /* Shadow paging assumes NX to be available. */ if (!enable_ept) @@ -988,17 +989,21 @@ static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) else clear_atomic_switch_msr(vmx, MSR_EFER); return false; - } else { - clear_atomic_switch_msr(vmx, MSR_EFER); - - guest_efer &= ~ignore_bits; - guest_efer |= host_efer & ignore_bits; - - vmx->guest_uret_msrs[efer_offset].data = guest_efer; - vmx->guest_uret_msrs[efer_offset].mask = ~ignore_bits; - - return true; } + + i = __vmx_find_uret_msr(vmx, MSR_EFER); + if (i < 0) + return false; + + clear_atomic_switch_msr(vmx, MSR_EFER); + + guest_efer &= ~ignore_bits; + guest_efer |= host_efer & ignore_bits; + + vmx->guest_uret_msrs[i].data = guest_efer; + vmx->guest_uret_msrs[i].mask = ~ignore_bits; + + return true; } #ifdef CONFIG_X86_32 @@ -1719,9 +1724,11 @@ static void setup_msrs(struct vcpu_vmx *vmx) move_msr_up(vmx, index, nr_active_uret_msrs++); } #endif - index = __vmx_find_uret_msr(vmx, MSR_EFER); - if (index >= 0 && update_transition_efer(vmx, index)) - move_msr_up(vmx, index, nr_active_uret_msrs++); + if (update_transition_efer(vmx)) { + index = __vmx_find_uret_msr(vmx, MSR_EFER); + if (index >= 0) + move_msr_up(vmx, index, nr_active_uret_msrs++); + } if (guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) { index = __vmx_find_uret_msr(vmx, MSR_TSC_AUX); if (index >= 0) -- 2.28.0