From: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
To: xiaoliang.yang_1@nxp.com, davem@davemloft.net,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
allan.nielsen@microchip.com, joergen.andreasen@microchip.com,
UNGLinuxDriver@microchip.com, alexandre.belloni@bootlin.com,
fido_max@inbox.ru, alexandru.marginean@nxp.com, po.liu@nxp.com,
claudiu.manoil@nxp.com, vladimir.oltean@nxp.com,
leoyang.li@nxp.com
Subject: [net] net: mscc: ocelot: fix fields offset in SG_CONFIG_REG_3
Date: Thu, 24 Sep 2020 10:11:13 +0800 [thread overview]
Message-ID: <20200924021113.9964-1-xiaoliang.yang_1@nxp.com> (raw)
INIT_IPS and GATE_ENABLE fields have a wrong offset in SG_CONFIG_REG_3.
This register is used by stream gate control of PSFP, and it has not
been used before, because PSFP is not implemented in ocelot driver.
Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
---
include/soc/mscc/ocelot_ana.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/soc/mscc/ocelot_ana.h b/include/soc/mscc/ocelot_ana.h
index 841c6ec22b64..1669481d9779 100644
--- a/include/soc/mscc/ocelot_ana.h
+++ b/include/soc/mscc/ocelot_ana.h
@@ -252,10 +252,10 @@
#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M GENMASK(18, 16)
#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(18, 16)) >> 16)
#define ANA_SG_CONFIG_REG_3_GATE_ENABLE BIT(20)
-#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << 24) & GENMASK(27, 24))
-#define ANA_SG_CONFIG_REG_3_INIT_IPS_M GENMASK(27, 24)
-#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & GENMASK(27, 24)) >> 24)
-#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(28)
+#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << 21) & GENMASK(24, 21))
+#define ANA_SG_CONFIG_REG_3_INIT_IPS_M GENMASK(24, 21)
+#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & GENMASK(24, 21)) >> 21)
+#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25)
#define ANA_SG_GCL_GS_CONFIG_RSZ 0x4
--
2.17.1
next reply other threads:[~2020-09-24 2:19 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-24 2:11 Xiaoliang Yang [this message]
2020-09-24 7:08 ` Alexandre Belloni
2020-09-24 8:49 ` [EXT] " Xiaoliang Yang
2020-09-25 3:02 ` David Miller
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