From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46119C4363D for ; Thu, 24 Sep 2020 10:52:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E0FB323977 for ; Thu, 24 Sep 2020 10:52:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726682AbgIXKwE (ORCPT ); Thu, 24 Sep 2020 06:52:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726415AbgIXKwE (ORCPT ); Thu, 24 Sep 2020 06:52:04 -0400 Received: from theia.8bytes.org (8bytes.org [IPv6:2a01:238:4383:600:38bc:a715:4b6d:a889]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6F75C0613CE for ; Thu, 24 Sep 2020 03:52:03 -0700 (PDT) Received: by theia.8bytes.org (Postfix, from userid 1000) id D8328295; Thu, 24 Sep 2020 12:52:01 +0200 (CEST) Date: Thu, 24 Sep 2020 12:52:00 +0200 From: Joerg Roedel To: Suravee Suthikulpanit Cc: linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Jon.Grimm@amd.com, brijesh.singh@amd.com Subject: Re: [PATCH v2 0/3] amd : iommu : Initial IOMMU support for SNP Message-ID: <20200924105200.GP27174@8bytes.org> References: <20200923121347.25365-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200923121347.25365-1-suravee.suthikulpanit@amd.com> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 23, 2020 at 12:13:44PM +0000, Suravee Suthikulpanit wrote: > Suravee Suthikulpanit (3): > iommu: amd: Use 4K page for completion wait write-back semaphore > iommu: amd: Add support for RMP_PAGE_FAULT and RMP_HW_ERR > iommu: amd: Re-purpose Exclusion range registers to support SNP CWWB Applied, thanks. I am slightly concerned about the re-purposing of the exclusion-range registers based on a feature bit being set. This makes the hardware incompatible to older IOMMU drivers which do not check the FEATURE_SNP bit. It will probably work in this case, as the firmware on systems with IOMMU-SNP support will not declare exclusion ranges at all and exclusion-ranges in the IOMMU hardware have been a bad idea since forever, but it would have been nicer if hardware actually provided a bit to enable this behavior. Regards, Joerg