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Sat, 26 Sep 2020 19:51:50 -0700 (PDT) Date: Sun, 27 Sep 2020 10:51:43 +0800 From: Leo Yan To: Andre Przywara Cc: Will Deacon , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Suzuki K Poulose , Tan Xiaojun , James Clark , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/5] arm64: spe: Allow new bits in SPE filter register Message-ID: <20200927025143.GA9677@leoy-ThinkPad-X240s> References: <20200922101225.183554-1-andre.przywara@arm.com> <20200922101225.183554-2-andre.przywara@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200922101225.183554-2-andre.przywara@arm.com> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Andre, On Tue, Sep 22, 2020 at 11:12:21AM +0100, Andre Przywara wrote: > The ARMv8.3-SPE extension adds some new bits for the event filter. > > Remove bits 11, 17 and 18 from the RES0 mask, so they can be used > correctly. > > Signed-off-by: Andre Przywara > --- > arch/arm64/include/asm/sysreg.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 554a7e8ecb07..efca4ee28671 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -281,7 +281,7 @@ > #define SYS_PMSFCR_EL1_ST_SHIFT 18 > > #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) > -#define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL > +#define SYS_PMSEVFR_EL1_RES0 0x0000ffff00f90755UL This patch is duplicate with Wei Li's patch [1]. You could see there have some discussion and Will gave suggestions [2] for the patch, this would be a good start point to continue this work. Thanks, Leo [1] https://www.spinics.net/lists/arm-kernel/msg825364.html [2] https://www.spinics.net/lists/arm-kernel/msg835733.html > > #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) > #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 > -- > 2.17.1 >